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MC68HC16Z1CPV16 Datasheet, PDF (327/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics | |||
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Freescale Semiconductor, Inc.
Table A-26 25.17-MHz ECLK Bus Timing
(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)1
Num
Characteristic
Symbol Min
Max
E1 ECLK Low to Address Valid2
tEAD
â
40
E2 ECLK Low to Address Hold
tEAH
10
â
E3 ECLK Low to CS Valid (CS Delay)
tECSD
â
100
E4 ECLK Low to CS Hold
tECSH
10
â
E5 CS Negated Width
tECSN
20
â
E6 Read Data Setup Time
tEDSR
25
â
E7 Read Data Hold Time
tEDHR
5
â
E8 ECLK Low to Data High Impedance
tEDHZ
â
40
E9 CS Negated to Data Hold (Read)
tECDH
0
â
E10 CS Negated to Data High Impedance
tECDZ
â
1
E11 ECLK Low to Data Valid (Write)
tEDDW
â
2
E12 ECLK Low to Data Hold (Write)
tEDHW
5
â
E13 CS Negated to Data Hold (Write)
E14 Address Access Time (Read)3
E15 Chip-Select Access Time (Read)4
tECHW
0
â
tEACC
255
â
tEACS
195
â
E16 Address Setup Time
tEAS
â
1/2
NOTES:
1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted.
2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = tEcyc â tEAD â tEDSR.
4. Chip select access time = tEcyc â tECSD â tEDSR.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tcyc
tcyc
ns
ns
ns
ns
tcyc
M68HC16 Z SERIES
USERâS MANUAL
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
A-43
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