MC68HC16Z1CPV16 Datasheet, PDF (114/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
When a fast reference is used, three W bits are located in the PLL feedback path, en-
abling frequency multiplication by a factor from one to eight. Three Y bits and the X bit
are located in the VCO clock output path to provide the ability to slow the system clock
without disturbing the PLL.
When using a fast reference, the clock frequency is determined by SYNCR bit settings
as follows:
f_sys
=
--^f--^r-^e---^f-
128
[4(Y
+
1)(2^(2W
+
X)_)]
The reset state of SYNCR ($3F00) results in a power-on f_sys of 8.388 MHz when f_ref
is 4.194 MHz.
For the device to perform correctly, both the clock frequency and VCO frequency (se-
lected by the W, X, and Y bits) must be within the limits specified for the MCU. In order
for the VCO frequency to be within specifications (less than or equal to the maximum
system clock frequency multiplied by two), the X bit must be set for system clock fre-
quencies greater than one-half the maximum specified system clock.
Internal VCO frequency is determined by the following equations:
f_VCO = 4f_sys if X = 0
or
f_VCO = 2f_sys if X = 1
On both slow and fast reference devices, when an external system clock signal is ap-
plied (MODCLK = 0 during reset), the PLL is disabled. The duty cycle of this signal is
critical, especially at operating frequencies close to maximum. The relationship be-
tween clock signal duty cycle and clock signal period is expressed as follows:
Minimum External Clock Period =
5----0---%-------–^{----P----e----r--c---eM---n--i-t-n-a--i-gm----e-u----mV----a--E-r--i-xa---t-t-ei--o-r--nn----a-o--l-f--C--E--l--ox---tc-e--k--r--n-H--a--i-gl---C-h---/-l-Lo---oc---wk-----I-T-n---ip--m--u---et-----D----u----t-y-----C----y---c---l--e-}
Tables 5-2, 5-3, and 5-4 show clock control multipliers for all possible combinations of
SYNCR bits. To obtain clock frequency, find the counter modulus in the leftmost col-
umn, then multiply the reference frequency by the value in the appropriate prescaler
cell. Shaded areas indicate which values exceed the specifications for a device rated
at a particular operating frequency. Refer to APPENDIX A ELECTRICAL CHARAC-
TERISTICS for maximum allowable clock rate.
Tables 5-5, 5-6, and 5-7 show actual clock frequencies for the same combinations of
SYNCR bits. To obtain clock frequency, find the counter modulus in the leftmost col-
umn, then refer to appropriate prescaler cell. Shaded areas indicate which values ex-
ceed the specifications for a device rated at a particular operating frequency. Refer to
APPENDIX A ELECTRICAL CHARACTERISTICS for maximum system frequency
(f ).
SYSTEM INTEGRATION MODULE
M68HC16 Z SERIES
5-8
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