MC68HC16Z1CPV16 Datasheet, PDF (104/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
4.14.4.6 BDM Serial Interface
The BDM serial interface uses a synchronous protocol similar to that of the Freescale
serial peripheral interface (SPI). Figure 4-7 is a diagram of the serial logic required to
use BDM with a development system.
CPU
INSTRUCTION
REGISTER BUS
16
RCV DATA LATCH
DEVELOPMENT SYSTEM
DATA
16
0
COMMAND LATCH
DSI
SERIAL IN
PARALLEL OUT
PARALLEL IN
SERIAL OUT
STATUS
EXECUTION
UNIT
SYNCHRONIZE
MICROSEQUENCER
PARALLEL IN
SERIAL OUT
16
DSO
SERIAL IN
PARALLEL OUT
STATUS
RESULT LATCH
16
DATA
CONTROL
LOGIC
DSCLK
CONTROL
LOGIC
Figure 4-7 BDM Serial I/O Block Diagram
SERIAL
CLOCK
BDM SER
COM BLOCK
The development system serves as the master of the serial link, and is responsible for
the generation of the serial interface clock signal (DSCLK).
Serial clock frequency range is from DC to one-half the CPU16 clock frequency. If
DSCLK is derived from the CPU16 system clock, development system serial logic can
be synchronized with the target processor.
The serial interface operates in full-duplex mode. Data transfers occur on the falling
edge of DSCLK and are stable by the following rising edge of DSCLK. Data is trans-
mitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide, which includes 16 data bits and a status/control
bit. Bit 16 indicates status of CPU-generated messages.
Command and data transfers initiated by the development system must clear bit 16.
All commands that return a result return 16 bits of data plus one status bit.
4-44
CENTRAL PROCESSING UNIT
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