MC68HC16Z1CPV16 Datasheet, PDF (387/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Time-out Period = ⁽---¹---²----⁸---⁾---⁽--^D----ⁱ--^v---ⁱ-^d---^e-----^R-----^a---^t--ⁱ-^o-----^S----^p---^e----^c---ⁱ-_ff--_rⁱ-^e_e---_f^d-----^b----^y----^S----^W------^P------^a---ⁿ---^d-----^S----^W------^T----^[--¹---^:--⁰---^]--⁾
The following equation calculates the time-out period for an externally input clock fre-
quency on both slow and fast reference frequency devices, when f_sys is equal to the
system clock frequency.
Time-out Period = ^D-----ⁱ-^v---ⁱ-^d----^e-----^R----^a---^t--ⁱ-^o-----^S----^p----^e---^c---ⁱ-^f--ⁱ-^e----^df--_s--_y-^b--_s-^y-----^S----^W-----^P------^a---ⁿ----^d-----^S----^W-----^T----^[--¹---^:--⁰---^]
HME — Halt Monitor Enable
0 = Halt monitor is disabled.
1 = Halt monitor is enabled.
BME — Bus Monitor External Enable
0 = Disable bus monitor for external bus cycles.
1 = Enable bus monitor for external bus cycles.
BMT[1:0] — Bus Monitor Timing
This field selects the bus monitor time-out period. Refer to Table D-7.
Table D-7 Bus Monitor Time-Out Period
BMT[1:0]
00
01
10
11
Bus Monitor Time-Out Period
64 system clocks
32 system clocks
16 system clocks
8 system clocks
D.2.13 Periodic Interrupt Control Register
PICR — Periodic Interrupt Control Register
$YFFA22
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
PIRQL[2:0]
PIV[7:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
PICR sets the interrupt level and vector number for the periodic interrupt timer (PIT).
Bits [10:0] can be read or written at any time. Bits [15:11] are unimplemented and al-
ways read zero.
PIRQL[2:0] — Periodic Interrupt Request Level
This field determines the priority of periodic interrupt requests. A value of %000 dis-
ables PIT interrupts.
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
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D-13