MC68HC16Z1CPV16 Datasheet, PDF (267/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Refer to D.8 General-Purpose Timer for a GPT address map and register bit/field de-
scriptions. Refer to 5.2.1 Module Mapping for more information about how the state
of MM affects the system.
11.3 Special Modes of Operation
The GPT module configuration register (GPTMCR) is used to control special GPT op-
erating modes. These include low-power stop mode, freeze mode, single-step mode,
and test mode. Normal GPT operation can be polled or interrupt-driven. Refer to 11.4
Polled and Interrupt-Driven Operation for more information.
11.3.1 Low-Power Stop Mode
Low-power stop operation is initiated by setting the STOP bit in GPTMCR. In stop
mode the system clock to the module is turned off. The clock remains off until STOP
is negated or a reset occurs. All counters and prescalers within the timer stop counting
while the STOP bit is set. Only the module configuration register (GPTMCR) and the
interrupt configuration register (ICR) should be accessed while in the stop mode. Ac-
cesses to other GPT registers cause unpredictable behavior. Low-power stop can also
be used to disable module operation during debugging.
11.3.2 Freeze Mode
The freeze (FRZ[1:0]) bits in GPTMCR are used to determine what action is taken by
the GPT when the IMB FREEZE signal is asserted. FREEZE is asserted when the
CPU enters background debug mode. At the present time, FRZ1 is not implemented;
FRZ0 causes the GPT to enter freeze mode. Refer to 4.14.4 Background Debug
Mode for more information.
Freeze mode freezes the current state of the timer. The prescaler and the pulse accu-
mulator do not increment and changes to the pins are ignored (input pin synchronizers
are not clocked). All of the other timer functions that are controlled by the CPU operate
normally. For example, registers can be written to change pin directions, force output
compares, and read or write I/O pins.
While the FREEZE signal is asserted, the CPU has write access to registers and bits
that are normally read-only or write-once. The write-once bits can be written to as often
as needed. The prescaler and the pulse accumulator remain stopped and the input
pins are ignored until the FREEZE signal is negated (the CPU is no longer in BDM),
the FRZ0 bit is cleared, or the MCU is reset.
Activities that are in progress before FREEZE assertion are completed. For example,
if an input edge on an input capture pin is detected just as the FREEZE signal is as-
serted, the capture occurs and the corresponding interrupt flag is set.
M68HC16 Z SERIES
USER’S MANUAL
GENERAL-PURPOSE TIMER
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