MC68HC16Z1CPV16 Datasheet, PDF (193/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
PRS[4:0]
%00000
%00001
%00010
%00011
…
%11101
%11110
%11111
Table 8-3 Prescaler Output
ADC Clock
Reserved
System Clock/4
System Clock/6
System Clock/8
…
System Clock/60
System Clock/62
System Clock/64
Minimum
System Clock
—
2.0 MHz
3.0 MHz
4.0 MHz
…
30.0 MHz
31.0 MHz
32.0 MHz
Maximum
System Clock
—
8.4 MHz
12.6 MHz
16.8 MHz
…
—
—
—
ADC clock speed must be between 0.5 MHz and 2.1 MHz. The reset value of the PRS
field is %00011, which divides a nominal 16.78 MHz system clock by eight, yielding
maximum ADC clock frequency. There are a minimum of four IMB clock cycles for
each ADC clock cycle.
8.7.3 Sample Time
The first two portions of all sample periods require four ADC clock cycles. During the
third portion of a sample period, the selected channel is connected directly to the RC
DAC array for a specified number of clock cycles. The value of the STS field in
ADCTL0 determines the number of cycles. Refer to Table 8-4. The number of clock
cycles required for a sample period is the value specified by STS plus four. Sample
time is determined by PRS value.
Table 8-4 TS Field Selection
STS[1:0]
00
01
10
11
Sample Time
2 A/D clock periods
4 A/D clock periods
8 A/D clock periods
16 A/D clock periods
8.7.4 Resolution
ADC resolution can be either eight or ten bits. Resolution is determined by the state of
the RES10 bit in ADCTL0. Both 8-bit and 10-bit conversion results are automatically
aligned in the result registers.
8.7.5 Conversion Control Logic
Analog-to-digital conversions are performed in sequences. Sequences are initiated by
any write to ADCTL1. If a conversion sequence is already in progress, a write to either
control register will abort it and reset the SCF and CCF flags in the A/D status register.
There are eight conversion modes. Conversion mode is determined by ADCTL1 con-
trol bits. Each conversion mode affects the bits in status register ADCSTAT differently.
Result storage differs from mode to mode.
M68HC16 Z SERIES
ANALOG-TO-DIGITAL CONVERTER
USER’S MANUAL
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8-7
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