MC68HC16Z1CPV16 Datasheet, PDF (398/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
D.3.2 RAM Test Register
RAMTST — RAM Test Register
Used for factory test only.
$YFFB02
D.3.3 Array Base Address Register High
RAMBAH — Array Base Address Register High (Z1, Z2, Z3, and Z4)
$YFFB04
15
8
7
6
5
4
3
2
1
0
RESET:
NOT USED
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
D.3.4 Array Base Address Register Low
RAMBAL — Array Base Address Register Low (1K SRAM — Z1/Z4)
$YFFB06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
15
RESET:
0
ADDR
14
0
ADDR
13
0
ADDR
12
0
ADDR
11
0
ADDR
10
0
ADDR
9
ADDR
8
ADDR
7
ADDR
6
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
ADDR
0
RAMBAL — Array Base Address Register Low (2K SRAM — Z2)
$YFFB06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
15
RESET:
0
ADDR
14
0
ADDR
13
0
ADDR
12
0
ADDR
11
0
ADDR
10
ADDR
9
ADDR
8
ADDR
7
ADDR
6
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
ADDR
0
RAMBAL — Array Base Address Register Low (4K SRAM — Z3)
$YFFB06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
15
RESET:
0
ADDR
14
0
ADDR
13
0
ADDR
12
0
ADDR
11
ADDR
10
ADDR
9
ADDR
8
ADDR
7
ADDR
6
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
ADDR
0
RAMBAH and RAMBAL specify the SRAM array base address in the system memory
map. They can only be written while the SRAM is in low-power stop mode (STOP = 1,
the default out of reset) and the base address lock is disabled (RLCK = 0, the default
out of reset). This prevents accidental remapping of the array. Because the CPU16
drives ADDR[23:20] to the same logic level as ADDR19, the values of RAMBAH
ADDR[23:20] must match the value of ADDR19 for the array to be accessible. These
registers may be read at any time. RAMBAH[15:8] are unimplemented and will always
read zero.
D-24
REGISTER SUMMARY
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M68HC16 Z SERIES
USER’S MANUAL