MC68HC16Z1CPV16 Datasheet, PDF (196/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Table 8-7 Single-Channel Conversions (MULT = 0)
S8CM
0
CD CC CB CA
0000
Input
AN0
Result Register¹
RSLT[0:3]
0
0001
AN1
RSLT[0:3]
0
0010
AN2
0
0011
AN3
RSLT[0:3]
RSLT[0:3]
0
0100
AN4
RSLT[0:3]
0
0101
AN5
0
0110
AN6
RSLT[0:3]
RSLT[0:3]
0
0111
AN7
RSLT[0:3]
0
1000
0
1001
Reserved
Reserved
RSLT[0:3]
RSLT[0:3]
0
1010
Reserved
RSLT[0:3]
0
1011
0
1100
0
1101
0
1110
0
1111
Reserved
V_RH
V_RL
(V_{RH –} V_RL) / 2
Test/Reserved
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
RSLT[0:3]
1
0000
AN0
1
0001
AN1
RSLT[0:7]
RSLT[0:7]
1
0010
AN2
RSLT[0:7]
1
0011
AN3
1
0100
AN4
1
0101
AN5
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
1
0110
1
0111
1
1000
AN6
AN7
Reserved
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
1
1001
1
1010
1
1011
Reserved
Reserved
Reserved
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
1
1100
1
1101
1
1110
1
1111
V_RH
V_RL
(V_{RH –} V_RL) / 2
Test/Reserved
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
RSLT[0:7]
NOTES:
1. Result register (RSLT) is either RJURRX, LJSRRX, or LJURRX, depending on the address read.
8-10
ANALOG-TO-DIGITAL CONVERTER
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