MC68HC16Z1CPV16 Datasheet, PDF (217/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
9.3.1.2 Status Register
SPSR contains information concerning the current serial transmission. Only the QSPI
can set the bits in this register. The CPU16 reads SPSR to obtain QSPI status infor-
mation and writes SPSR to clear status flags.
9.3.2 QSPI RAM
The QSPI contains an 80-byte block of dual-ported static RAM that can be accessed
by both the QSPI and the CPU16. The RAM is divided into three segments: receive
data RAM, transmit data RAM, and command data RAM. Receive data is information
received from a serial device external to the MCU. Transmit data is information stored
for transmission to an external device. Command control data defines transfer param-
eters. Refer to Figure 9-3, which shows RAM organization.
500
RR0
RR1
RR2
RECEIVE
RAM
RRD
RRE
51E
RRF
WORD
520
TR0
TR1
TR2
TRANSMIT
RAM
TRD
TRE
53E
TRF
WORD
540
CR0
CR1
CR2
COMMAND
RAM
CRD
CRE
54F
CRF
BYTE
Figure 9-3 QSPI RAM
QSPI RAM MAP
9.3.2.1 Receive RAM
Data received by the QSPI is stored in this segment to be read by the CPU16. Data
stored in the receive RAM is right-justified. Unused bits in a receive queue entry are
set to zero by the QSPI upon completion of the individual queue entry. The CPU16 can
access the data using byte, word, or long-word transfers.
The CPTQP value in SPSR shows which queue entries have been executed. The
CPU16 can use this information to determine which locations in receive RAM contain
valid data before reading them.
9.3.2.2 Transmit RAM
Data that is to be transmitted by the QSPI is stored in this segment and must be written
by the CPU16 in right-justified form. The QSPI cannot modify information in the trans-
mit RAM. The QSPI copies the information to its data serializer for transmission. Infor-
mation remains in the transmit RAM until overwritten.
M68HC16 Z SERIES
QUEUED SERIAL MODULE
USER’S MANUAL
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