MC68HC16Z1CPV16 Datasheet, PDF (282/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
11.11.1 PWM Counter
The 16-bit counter in the PWM unit is similar to the timer counter in the capture/com-
pare unit. During reset, the GPT is configured to use the system clock divided by two
to drive the counter. Initialization software can reconfigure the counter to use one of
seven prescaler outputs or an external clock input from the PCLK pin.
The PWM count register (PWMCNT) can be read at any time without affecting its val-
ue. A read must be a word access to ensure coherence, but byte accesses can be
made if coherence is not needed. The counter is cleared to $0000 during reset and is
a read-only register except in freeze or test mode.
Fifteen of the sixteen counter bits are output to multiplexers A and B. The multiplexers
provide the fast and slow modes of the PWM unit. Mode for PWMA is selected by the
SFA bit in the PWM control register C (PWMC). Mode for PWMB is selected by the
SFB bit in the same register.
PWMA, PWMB, and PPR[2:0] bits in PWMC control PWM output frequency. In fast
mode, bits [7:0] of PWMCNT are used to clock the PWM logic; in slow mode, bits [14:7]
are used. The period of a PWM output in slow mode is 128 times longer than the fast
mode period. Table 11-3 shows a range of PWM output frequencies using 16.78 MHz,
20.97 MHz, and 25.17 MHz system clocks.
Table 11-3 PWM Frequency Ranges
PPR
[2:0]
16.78 MHz
Prescaler Tap
20.97 MHz
25.17 MHz
SFA/B = 0
16.78 MHz 20.97 MHz 25.17 MHz 16.78 MHz
000 Div 2 = 8.39 MHz Div 2 = 10.5 MHz Div 2 = 12.6 MHz 32.8 kHz 41 kHz 49.2 kHz 256 Hz
001 Div 4 = 4.19 MHz Div 4 = 5.25 MHz Div 4 = 6.29 MHz 16.4 kHz 20.5 kHz 24.6 kHz 128 Hz
010 Div 8 = 2.10 MHz Div 8 = 2.62 MHz Div 8 = 3.15 MHz 8.19 kHz 10.2 kHz 12.3 kHz 64.0 Hz
011 Div 16 = 1.05 MHz Div 16 = 1.31 MHz Div 16 = 1.57 MHz 4.09 kHz 5.15 kHz 6.13 kHz 32.0 Hz
100 Div 32 = 524 kHz Div 32 = 655 kHz Div 32 = 787 kHz 2.05 kHz 2.56 kHz 3.07 kHz 16.0 Hz
101 Div 64 = 262 kHz Div 64 = 328 kHz Div 64 = 393 kHz 1.02 kHz 1.28 kHz 1.54 kHz 8.0 Hz
110 Div 128 = 131 kHz Div 128 = 164 kHz Div 128 = 197 kHz 512 Hz 641 Hz 770 Hz
4.0 Hz
111
PCLK
PCLK
PCLK
PCLK/256 PCLK/256 PCLK/256
PCLK/
32768
SFA/B = 1
20.97 MHz
320 Hz
160 Hz
80.0 Hz
40.0 Hz
20.0 Hz
10.0 Hz
5.0 Hz
PCLK/
32768
25.17 MHz
384 Hz
192 Hz
96 Hz
48 Hz
24 Hz
12 Hz
6 Hz
PCLK/
32768
11.11.2 PWM Function
The pulse width values of the PWM outputs are determined by control registers PWMA
and PWMB. PWMA and PWMB are 8-bit registers implemented as two bytes of a 16-
bit register. PWMA and PWMB can be accessed as separate bytes or as one 16-bit
register. A value of $00 loaded into either register causes the corresponding output pin
to output a continuous logic level zero signal. A value of $80 causes the corresponding
output signal to have a 50% duty cycle, and so on, to the maximum value of $FF, which
corresponds to an output which is at logic level one for 255/256 of the cycle.
Setting the F1A (for PWMA) or F1B (for PWMB) bits in the CFORC register causes the
corresponding pin to output a continuous logic level one signal. The logic level of the
associated pin does not change until the end of the current cycle. F1A and F1B are
the lower two bits of CFORC, but can be accessed at the same word address as
PWMC.
11-18
GENERAL-PURPOSE TIMER
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