MC68HC16Z1CPV16 Datasheet, PDF (419/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
D.6.9 Port QS Pin Assignment Register/Data Direction Register
PQSPAR — PORT QS Pin Assignment Register
DDRQS — PORT QS Data Direction Register
$YFFC16
$YFFC17
15
14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
NOT
USED
PQSPA6
PQSPA5
PQSPA4
PQSPA3
NOT
USED
PQSPA1
PQSPA0
DDQS7
DDQS6
DDQS5
DDQS4
DDQS3
DDQS2
DDQS1
DDQS0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O. Set-
ting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI.
Table D-33 displays PQSPAR pin assignments.
Table D-33 PQSPAR Pin Assignments
PQSPAR Field
PQSPA0
PQSPA1
PQSPAR Bit
0
1
0
1
Pin Function
PQS0
MISO
PQS1
MOSI
—
—
PQS2¹
—
SCK
PQSPA3
0
1
PQS3
PCS0/SS
PQSPA4
0
1
PQS4
PCS1
PQSPA5
0
1
PQS5
PCS2
PQSPA6
0
1
PQS6
PCS3
—
—
PQS7²
—
TXD
NOTES:
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE set in
SPCR1), in which case it becomes the QSPI serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE set
in SCCR1), in which case it becomes the SCI serial output TXD.
DDRQS determines whether pins configured for general-purpose I/O are inputs or out-
puts. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin
an output. DDRQS affects both QSPI function and I/O function.Table D-34 shows the
effect of DDRQS on QSM pin function.
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
For More Information On This Product,
Go to: www.freescale.com
D-45