MC68HC16Z1CPV16 Datasheet, PDF (394/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Table D-15 DSACK Field Encoding
DSACK[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Clock Cycles Required
Per Access
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
—
Wait States Inserted
Per Access
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Fast Termination
External DSACK
External memories are purchased with guaranteed access times on speed (in nano-
seconds). Table D-16 relates wait states selected by DSACK[3:0] to the memory de-
vice access time.
NOTE
Table D-16 assumes a system configuration that minimizes power
consumption and the number of chip-selects employed. Other ac-
cess techniques can provide the same access times with slower
memory devices, but require more chip-selects to be used and will
subsequently increase system power consumption.
Table D-16 Memory Access Times at 16.78, 20.97, and 25.17 MHz
Speed
16.78 MHz
20.97 MHz
25.17 MHz
t_cyc
62.5 ns
50.0 ns
40.0 ns
Fast Termination Access Time
30.0 ns
20.0 ns
15.0 ns
0 Wait State
95.0 ns
70.0 ns
55.0 ns
1 Wait State
155.0 ns
120.0 ns
95.0 ns
D-20
REGISTER SUMMARY
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