MC68HC16Z1CPV16 Datasheet, PDF (61/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
SECTION 4
CENTRAL PROCESSOR UNIT
This section is an overview of the central processor unit (CPU16). For detailed infor-
mation, refer to the CPU16 Reference Manual (CPU16RM/AD).
4.1 General
The CPU16 provides compatibility with the M68HC11 CPU and also provides addition-
al capabilities associated with 16- and 32-bit data sizes, 20-bit addressing, and digital
signal processing. CPU16 registers are an integral part of the CPU and are not ad-
dressed as memory locations.
The CPU16 treats all peripheral, I/O, and memory locations as parts of a linear one
Megabyte address space. There are no special instructions for I/O that are separate
from instructions for addressing memory. Address space is made up of sixteen 64-
Kbyte banks. Specialized bank addressing techniques and support registers provide
transparent access across bank boundaries.
The CPU16 interacts with external devices and with other modules within the micro-
controller via a standardized bus and bus interface. There are bus protocols used for
memory and peripheral accesses, as well as for managing a hierarchy of interrupt
priorities.
4.2 Register Model
Figure 4-1 shows the CPU16 register model. Refer to the paragraphs that follow for a
detailed description of each register.
M68HC16 Z SERIES
CENTRAL PROCESSOR UNIT
USER’S MANUAL
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4-1
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