MC68HC16Z1CPV16 Datasheet, PDF (436/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
TE — Transmitter Enable
0 = SCI transmitter disabled (TXD pin can be used as I/O).
1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter).
RE — Receiver Enable
0 = SCI receiver disabled.
1 = SCI receiver enabled.
RWU — Receiver Wake-Up
0 = Normal receiver operation (received data recognized).
1 = Wake-up mode enabled (received data ignored until receiver is awakened).
SBK — Send Break
0 = Normal operation
1 = Break frame(s) transmitted after completion of the current frame.
D.7.11 SCI Status Register
SCSRA — SCIA Status Register
SCSRB — SCIB Status Register
$YFFC1C
$YFFC2C
15
RESET:
NOT USED
9
8
7
6
5
4
3
2
1
0
TDRE TC RDRF RAF IDLE OR NF FE PF
1
1
0
0
0
0
0
0
0
SCSR contains flags that show SCI operating conditions. These flags are cleared ei-
ther by SCI hardware or by a read/write sequence. The sequence consists of reading
SCSR, then reading or writing SCDR.
If an internal SCI signal for setting a status bit comes after reading the asserted status
bits, but before writing or reading SCDR, the newly set status bit is not cleared. SCSR
must be read again with the bit set and SCDR must be read or written before the status
bit is cleared.
A long-word read can consecutively access both SCSR and SCDR. This action clears
receive status flag bits that were set at the time of the read, but does not clear TDRE
or TC flags. Reading either byte of SCSR causes all 16 bits to be accessed, and any
status bit already set in either byte is cleared on a subsequent read or write of SCDR.
Bits [15:9] — Not Implemented
TDRE — Transmit Data Register Empty
0 = Transmit data register still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to the transmit data register.
TC — Transmit Complete
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
D-62
REGISTER SUMMARY
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