MC68HC16Z1CPV16 Datasheet, PDF (412/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
D.6 Queued Serial Module
Table D-31 QSM Address Map
Address¹ 15
87
0
$YFFC00
QSM Module Configuration Register (QSMCR)
$YFFC02
QSM Test Register (QTEST)
$YFFC04
QSM Interrupt Level Register (QILR)
QSM Interrupt Vector Register (QIVR)
$YFFC06
Not Used
$YFFC08
SCI Control 0 Register (SCCR0)
$YFFC0A
SCI Control 1 Register (SCCR1)
$YFFC0C
SCI Status Register (SCSR)
$YFFC0E
SCI Data Register (SCDR)
$YFFC10
Not Used
$YFFC12
Not Used
$YFFC14
Not Used
Port QS Data Register (PORTQS)
$YFFC16
Port QS Pin Assignment Register
(PQSPAR)
Port QS Data Direction Register (DDRQS)
$YFFC18
SPI Control Register 0 (SPCR0)
$YFFC1A
SPI Control Register 1 (SPCR1)
$YFFC1C
SPI Control Register 2 (SPCR2)
$YFFC1E
SPI Control Register 3 (SPCR3)
SPI Status Register (SPSR)
$YFFC20 –
$YFFCFF
Not Used
$YFFD00 –
$YFFD1F
Receive RAM (RR[0:F])
$YFFD20 –
$YFFD3F
Transmit RAM (TR[0:F])
$YFFD40 –
$YFFD4F
Command RAM (CR[0:F])
NOTES:
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D.6.1 QSM Configuration Register
QSMCR — QSM Configuration Register
$YFFC00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP FRZ1 FRZ0
NOT USED
SUPV
NOT USED
IARB[3:0]
RESET:
0
0
0
1
0
0
0
0
QSMCR bits enable stop and freeze modes, and determine the arbitration priority of
QSM interrupt requests.
D-38
REGISTER SUMMARY
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M68HC16 Z SERIES
USER’S MANUAL