MC68HC16Z1CPV16 Datasheet, PDF (162/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the
clock is running and MSTRST is asserted for at least four clock cycles, these modules
reset. V_DD ramp time and VCO frequency ramp time determine how long the four cy-
cles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.
Figure 5-20 is a timing diagram for power-on reset. It shows the relationships between
RESET, V_DD, and bus signals.
CLKOUT
VCO
LOCK
V_DD
RESET
2 CLOCKS
512 CLOCKS
10 CLOCKS
BUS
CYCLES
ADDRESS AND
BUS STATE
UNKNOWN
CONTROL SIGNALS
THREE-STATED
1
NOTES:
1. INTERNAL START-UP TIME
2. FIRST INSTRUCTION FETCHED
Figure 5-20 Power-On Reset
2
16 POR TIM
5.7.8 Use of the Three-State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers
in a disabled, high-impedance state. The signal must remain asserted for approxi-
mately ten clock cycles in order for drivers to change state.
When the internal clock synthesizer is used (MODCLK held high during reset), synthe-
sizer ramp-up time affects how long the ten cycles take. Worst case is approximately
20 milliseconds from TSC assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to
high-impedance state as soon after TSC assertion as approximately ten clock pulses
have been applied to the EXTAL pin.
5-56
SYSTEM INTEGRATION MODULE
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M68HC16 Z SERIES
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