MC68HC16Z1CPV16 Datasheet, PDF (192/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
8.6.4 Comparator
The comparator indicates whether each approximation output from the RC DAC array
during resolution is higher or lower than the sampled input voltage. Comparator output
is fed to the digital control logic, which sets or clears each bit in the successive approx-
imation register in sequence, MSB first.
8.7 Digital Control Subsystem
The digital control subsystem includes control and status registers, clock and prescal-
er control logic, channel and reference select logic, conversion sequence control logic,
and the successive approximation register.
The subsystem controls the multiplexer and the output of the RC array during sample
and conversion periods, stores the results of comparison in the successive-approxi-
mation register, then transfers results to the result registers.
8.7.1 Control/Status Registers
There are two control registers (ADCTL0, ADCTL1) and one status register
(ADCSTAT). ADCTL0 controls conversion resolution, sample time, and clock/prescal-
er value. ADCTL1 controls analog input selection, conversion mode, and initiation of
conversion. A write to ADCTL0 aborts the current conversion sequence and halts the
ADC. Conversion must be restarted by writing to ADCTL1. A write to ADCTL1 aborts
the current conversion sequence and starts a new sequence with parameters altered
by the write. ADCSTAT shows conversion sequence status, conversion channel sta-
tus, and conversion completion status.
The following paragraphs are a general discussion of control function. D.5 Analog-to-
Digital Converter Module shows the ADC address map and discusses register bits
and fields.
8.7.2 Clock and Prescaler Control
The ADC clock is derived from the system clock by a programmable prescaler. ADC
clock period is determined by the value of the PRS field in ADCTL0. The prescaler has
two stages. The first stage is a 5-bit modulus counter. It divides the system clock by
any value from two to 32 (PRS[4:0] = %00000 to %11111). The second stage is a di-
vide-by-two circuit. Table 8-3 shows prescaler output values.
ANALOG-TO-DIGITAL CONVERTER
M68HC16 Z SERIES
8-6
For More Information On This Product,
USER’S MANUAL
Go to: www.freescale.com