MC68HC16Z1CPV16 Datasheet, PDF (208/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
In Figure 8-10, R_F and C_F comprise the user's external filter circuit. C_S is the internal
sample capacitor. Each channel has its own capacitor. C_S is never precharged; it re-
tains the value of the last sample. V_I is an internal voltage source used to precharge
the DAC capacitor array (C_DAC) before each sample. The value of this supply is V_DDA/
2, or 2.5 volts for 5-volt operation.
The following paragraphs provide a simplified description of the interaction between
the ADC and the user's external circuitry. This circuitry is assumed to be a simple RC
low-pass filter passing a signal from a source to the ADC input pin. The following sim-
plifying assumptions are made:
• The source impedance is included with the series resistor of the RC filter.
• The external capacitor is perfect (no leakage, no significant dielectric absorption
characteristics, etc.)
• All parasitic capacitance associated with the input pin is included in the value of
the external capacitor.
• Inductance is ignored.
• The “on” resistance of the internal switches is zero ohms and the “off” resistance
is infinite.
8.8.6.1 Settling Time for the External Circuit
The values for R_F and C_F in the user's external circuitry determine the length of time
required to charge C_F to the source voltage level (V_SRC).
At time t = 0, S1 in Figure 8-10 closes. S2 is open, disconnecting the internal circuitry
from the external circuitry. Assume that the initial voltage across CF is zero. As CF
charges, the voltage across it is determined by the following equation, where t is the
total charge time:
V_CF = V_SRC(1 – e^{–t ⁄ RFCF})
When t = 0, the voltage across C_F = 0. As t approaches infinity, V_CF will equal V_SRC.
(This assumes no internal leakage.) With 10-bit resolution, 1/2 of a count is equal to
1/2048 full-scale value. Assuming worst case (V_SRC = full scale), Table 8-10 shows
the required time for C_F to charge to within 1/2 of a count of the actual source voltage
during 10-bit conversions. Table 8-10 is based on the RC network in Figure 8-10.
NOTE
The following times are completely independent of the A/D converter
architecture (assuming the ADC is not affecting the charging).
8-22
ANALOG-TO-DIGITAL CONVERTER
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M68HC16 Z SERIES
USER’S MANUAL