MC68HC16Z1CPV16 Datasheet, PDF (132/500 Pages) Freescale Semiconductor, Inc – Symbols and Operators, CPU16 Register Mnemonics

Freescale Semiconductor, Inc.
Both writes must occur before time-out in the order listed. Any number of instructions
can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) bit and the
software watchdog timing (SWT[1:0]) field in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be select-
ed. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in Table 5-9. System software can change SWP value.
Table 5-9 MODCLK Pin and SWP Bit During Reset
MODCLK
0 (External Clock)
1 (Internal Clock)
SWP
1 (÷ 512)
0 (÷ 1)
SWT[1:0] selects the divide ratio used to establish the software watchdog time-out
period.
The following equation calculates the time-out period for a slow reference frequency,
where f_ref is equal to the EXTAL crystal frequency.
Time-Out Period = ^D-----ⁱ-^v---ⁱ-^d----^e-----^R----^a---^t--ⁱ-^o-----^S----^p----^e---^c---ⁱ-^f--ⁱ-^e----^d-----^b---^y-----^S----^W-----^P------^a---ⁿ----^d-----^S----^W-----^T----^[--¹---^:--⁰---^]
f_ref
The following equation calculates the time-out period for a fast reference frequency,
where f_ref is equal to the EXTAL crystal frequency.
Time-Out Period = -⁽--¹---²----⁸---⁾---⁽--^D----ⁱ--^v---ⁱ-^d---^e-----^R-----^a---^t--ⁱ-^o-----^S----^p---^e----^c---ⁱ-_ff--_rⁱ-^e_e---_f^d-----^b----^y----^S----^W------^P------^a---ⁿ---^d-----^S----^W------^T----^[--¹---^:--⁰---^]--⁾
The following equation calculates the time-out period for an externally input clock fre-
quency on both slow and fast reference frequency devices, when f_sys is equal to the
system clock frequency.
Time-Out Period = ^D-----ⁱ-^v---ⁱ-^d----^e-----^R----^a---^t--ⁱ-^o-----^S----^p----^e---^c---ⁱ-^f--ⁱ-^e----^df--_s--_y-^b--_s-^y-----^S----^W-----^P------^a---ⁿ----^d-----^S----^W-----^T----^[--¹---^:--⁰---^]
Table 5-10 shows the divide ratio for each combination of SWP and SWT[1:0] bits.
When SWT[1:0] are modified, a watchdog service sequence must be performed be-
fore the new time-out period can take effect.
5-26
SYSTEM INTEGRATION MODULE
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