XRT72L53 Datasheet, PDF (9/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
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PRELIMINARY
PIN DESCRIPTION CONNECTED PINS
PIN #
B17
PIN NAME
TxNibFrame[1]/
ValFCS[1]
B18
RxFrame[1]
B19
RxNib0[1]/
RxHDLCDat0[1]
B20
RxNib2[1]/
RxHDLCDat2[1]
C1
TxPOS[0]
TYPE
O
O
O
O
O
DESCRIPTION
Transmit Frame Boundary Indicator - Nibble-Parallel Interface/
Transmit HDLC - VALID FRAME CHECK SEQUENCE Indicator -
Channel 1:
See Description for Pin G17
Receive Boundary of DS3 or E3 Frame Output Indicator - Channel
1:
See Description for Pin F20
Receive Nibble Output - Bit 0/Receive HDLC Data Output - Bit 0;
Channel 1:
See Description for Pin G19
Receive Nibble Output - Bit 2/Receive HDLC Data Output - Bit 2;
Channel 1:
See Description for Pin H18
Transmit Positive Polarity Pulse output - Channel 0:
The exact role of this output pin depends upon whether Channel 0 is
operating in the Single-Rail or Dual-Rail Mode.
Single-Rail Mode:
This output pin functions as the Single-Rail output signal for the out-
bound DS3 or E3 data stream. The signal, at this output pin, will be
updated on the user-selected edge of the TxLineClk signal.
C2
TCK
Dual-Rail Mode:
This output pin functions as one of the two dual rail output signals that
commands the sequence of pulses to be driven on the line. TxNEG[0] is
the other output pin. This input is typically connected to the TPDATA
input of the external DS3 or E3 Line Interface Unit IC. When this output
is asserted, it will command the LIU to generate a positive polarity pulse
on the line
I
Test Clock:
Boundary Scan clock input.
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