XRT72L53 Datasheet, PDF (81/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
ceive DS3/E3 Framer block. This bit is cleared to "0"
when the FEAC code is removed.
NOTE: For more information on the role of this bit-field and
the Receive FEAC Processor, please see Section 3.3.3.1.
Bit 3 - RxFEAC Remove Interrupt Enable
This Read/Write bit-field is used to enable/disable the
RxFEAC Removal interrupt. Writing a "1" to this bit
enables this interrupt. Likewise, writing a "0" to this
bit-field disables this interrupt.
NOTE: For more information on the role of this bit-field and
the Receive FEAC Processor, please see Section 3.3.3.1.
Bit 2 - RxFEAC Remove Interrupt Status
A "1" in this Read Only bit-field indicates that the
most recently received and validated FEAC Message
has now been removed by the Receive FEAC Proces-
sor. The Receive FEAC Processor will remove a vali-
dated FEAC message if 3 out of the last 10 received
FEAC messages differ from the latest valid FEAC
Message.
NOTE: For more information on this bit-field and the
Receive FEAC Processor, please see Section 3.3.3.1.
Bit 1 - RxFEAC Valid Interrupt Enable
This Read/Write bit-field is used to enable or disable
the Rx FEAC Valid interrupt. Writing a "1" to this bit-
field enables this interrupt. Whereas, writing a "0" dis-
ables this interrupt. The value of this bit-field is "0" fol-
lowing power up or reset.
NOTE: For more information on this bit-field and the
Receive FEAC Processor, please see Section 3.3.3.1.
Bit 0 - RxFEAC Valid Interrupt Status
A "1" in this Read Only bit-field indicates that a newly
received FEAC Message has been validated by the
Receive FEAC Processor.
The Receive FEAC Processor will validate a new
FEAC message, once that message has been re-
ceived in 8 out of 10 most recently received FEAC
Messages.
NOTE: For more information on this bit-field and the
Receive FEAC Processor, please see Section 3.3.3.1.
2.4.2.14 Receive DS3 LAPD Control Register
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
RxLAPD
Enable
RxLAPD
Interrupt
Enable
RxLAPD
Interrupt
Status
RO
RO
RO
RO
RO
R/W
R/W
RUR
0
0
0
0
0
0
0
0
Bit 2 RxLAPD Enable
This Read/Write bit-field is used to enable or disable
the LAPD Receiver. The LAPD Receiver MUST be
enabled before it can begin to receive and process
any LAPD Message frames from the incoming DS3
data stream.
Writing a "0" to this bit-field disables the LAPD Re-
ceiver (the default condition). Writing a "1" to this bit-
field enables the LAPD Receiver.
Bit 1 RxLAPD (Message Frame Reception Com-
plete) Interrupt Enable
This Read/Write bit-field is used to enable or disable
the LAPD Message Frame Reception Complete inter-
rupt. If this interrupt is enabled, then the channel
(within the Framer IC) will generate this interrupt to
the local µP, once the last bit of a LAPD Message
frame has been received and the PMDL message
has been extracted and written into the Receive
LAPD Message buffer.
Writing a "0" to this bit-field disables this interrupt (the
default condition). Writing a "1" to this bit-field en-
ables this interrupt.
Bit 0 RxLAPD (Message Reception Complete) In-
terrupt Status
This Read-Only bit field indicates whether or not the
LAPD Message Reception Complete interrupt has
occurred since the last read of this register. The
LAPD Message Reception Complete interrupt will oc-
cur once the LAPD Receiver has received the last bit
of a complete LAPD Message frame, extracted the
PMDL message from this LAPD Message frame and
has written this (PMDL) message frame into the Re-
ceive LAPD Message buffer. The purpose of this in-
terrupt is to notify the local µP that the Receive LAPD
Message buffer contains a new PMDL message, that
needs to be read and/or processed.
A "0" in this bit-field indicates that the LAPD Message
Reception Complete interrupt has NOT occurred
since the last read of this register. A "1" in this bit-field
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