XRT72L53 Datasheet, PDF (66/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L53
REV. P1.1.7
2.3.2.2.2.2.2 The Subsequent Write Operations
The procedure that the µC/µP must use to perform
the remaining write cycles, within this burst access
operation, is presented below.
B.0 Execute each subsequent write cycle, as
described in Steps B.1 through B.3
B.1 Without toggling the ALE_AS (Address Strobe)
input pin (e.g., keeping it "High"), apply the
value of the next byte or word (to be written into
the Framer) to the bi-directional data bus pins,
D[7:0].
B.2 Toggle the RD_DS (Data Strobe) input pin
"Low". This step accomplishes the following.
a. The Framer internally increments the latched
address value (within the Microprocessor Inter-
face).
b. The input drivers of the bi-directional data bus are
enabled.
NOTE: In order to insure that the XRT72L53 DS3/E3
Framer will interpret this signal as being a Write signal, the
µC/µP should keep the WR_R/W input pin "Low".
B.3 After some settling time, the data, in the inter-
nal data bus, will stabilize and is ready to be
latched into the Framer Microprocessor Inter-
face block. The Microprocessor Interface block
will indicate that this data is ready to be latched
by asserting the RDY_DTCK (DTACK) output
signal. At this point, the µC/µP should latch the
data into the Framer by toggling the RD_DS
input pin "High".
For subsequent write operations, within this burst I/O
access, the µC/µP simply repeats steps B.1 through
B.3 as illustrated in Figure 36.
FIGURE 36. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT WRITE OPERATIONS
WITH THE BURST I/O CYCLE (MOTOROLA-TYPE µC/µP)
ALE_AS
A(10:0)
Address of "Initial" Target Register (Offset = 0x00)
CS
D(7:0)
Data Written at Offset = 0x01
Data Written at Offset = 0x02
RD_DS
WR_R/W
RDY_DTCK
2.3.2.2.2.2.3 Terminating the Burst I/O Access
The Burst I/O Access will be terminated upon the fall-
ing edge of the ALE_AS input signal. At this point the
Framer will cease to internally increment the latched
address value. Further, the µC/µP is now free to exe-
cute either a Programmed I/O access or to start an-
other Burst I/O Access with the XRT72L53 DS3/E3
Framer.
2.4 ON-CHIP REGISTER ORGANIZATION
The Microprocessor Interface section, within the
Framer allows the user to do the following.
• Configure the Framer into a wide variety of operat-
ing modes.
• Employ various features of the Framer.
• Perform status monitoring
• Enable/Disable and service Interrupt Conditions
All of these things are accomplished by reading from
and writing to the many on-chip registers within the
Framer. Table 5 lists each of these registers and their
corresponding address locations within the Framer
Address space.
2.4.1 Framer Register Addressing
The array of on-chip registers consists of a variety of
register types. These registers are denoted in
Table 5, as follows.
R/O - Read Only Registers.
R/W - Read/Write Registers
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