XRT72L53 Datasheet, PDF (131/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
Conversely, if this bit-field contains a logic “0”, then
the RLOL input pin is "Low". The DS3/E3 LIU IC will
hold this pin "Low" as long as this clock recovery
phase-locked-loop circuitry (within the LIU) is proper-
ly locked onto the incoming DS3 or E3 data-stream,
and is properly recovering clock and data from this
data-stream.
For more information on the operation of these Exar
XRT73L0X-type of DS3/E3/STS-1 LIU IC’s, please
consult any of the following data sheets.
• XRT7300 1-Channel DS3/E3/STS-1 LIU IC (5V)
• XRT73L00 1-Channel DS3/E3/STS-1 LIU IC (3.3V)
• XRT7302 2-Channel DS3/E3/STS-1 LIU IC (5V)
• XRT73L03 3-Channel DS3/E3/STS-1 LIU IC (3.3V)
• XRT73L04 4-Channel DS3/E3/STS-1 LIU IC (3.3V)
NOTE: If the customer is not using an Exar XRT73L0X-
type of DS3/E3/STS-1 IC, then this bit-field, and the
RLOL[n] input pin can be used for other purposes.
Bit 0 - RLOS - (Receive Loss of Signal)
This Read-Only bit-field indicates the logic state of
the RLOS[n] input pin of the Framer. This input pin is
intended to be connected to the RLOS output pin of
the DS3/E3 LIU IC. If this bit-field contains a logic "1",
then the RLOS[n] input pin is "High". The LIU will tog-
gle this signal "High" if it (the LIU IC) is currently de-
claring an LOS (Loss of Signal) condition.
Conversely, if this bit-field contains a logic "0", then
the RLOS input pin is "Low". The LIU will hold this
signal "Low" if it is NOT currently declaring an LOS
(Loss of Signal) condition.
For more information on the LOS Declaration and
Clearance criteria within the Exar XRT73L0X type of
DS3/E3/STS-1 LIU IC, please consult any of the fol-
lowing data sheets.
• XRT7300 1-Channel DS3/E3/STS-1 LIU IC (5V)
• XRT73L00 1-Channel DS3/E3/STS-1 LIU IC (3.3V)
• XRT7302 2-Channel DS3/E3/STS-1 LIU IC (5V)
• XRT73L03 3-Channel DS3/E3/STS-1 LIU IC (3.3V)
• XRT73L04 4-Channel DS3/E3/STS-1 LIU IC (3.3V)
NOTE: Asserting the RLOS input pin will cause the
XRT72L53 Framer IC to generate the Change in LOS Con-
dition interrupt and declare an LOS (Loss of Signal) condi-
tion. Therefore, this input pin should not be used as a gen-
eral purpose input.
2.4.8.21 HDLC Control Register
HDLC CONTROL REGISTER (ADDRESS = 0X82)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Framer
By-Pass
HDLC
ON
CRC-32
Select
Reserved
HDLC
Loop-Back
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 - Framer By-Pass
This Read/Write bit-field is used to enable or disable
(by-pass) the DS3/E3 Framer circuitry, within a given
channel in the XRT72L53.
This feature is used to operate a given Channel in the
Un-framed Mode. Further, this feature also is used to
transmit and receive HDLC frames at the DS3 or E3
line rate of 44.736Mbps or 34.368Mbps, without sac-
rificing any bandwidth to support the overhead bits/
bytes/
Setting this bit-field to “1” disables the Transmit and
Receive DS3/E3 Framer blocks within the channel.
Setting this bit-field to “0” enables the Transmit and
Receive DS3/E3 Framer blocks.
Bit 6 - HDLC ON
This Read/Write bit-field is used to configure a given
channel to operate in the High-Speed HDLC Control-
ler Mode. If the user invokes this feature, then a
Transmit and Receive byte-wide interface will be en-
abled, and the channel will be configured to transmit
and receive HDLC Frames via the DS3 or E3 payload
bits.
Setting this bit-field to “1” configures the channel to
operate in the High-Speed HDLC Controller Mode.
Bit 5 - CRC-32
This Read/Write bit-field is used to configure a given
channel to do the following.
1. To configure the Transmit HDLC Controller block
to compute and append either a CRC-16 or a
CRC-32 value as a trailer to the outbound HDLC
frame.
2. To configure the Receive HDLC Controller block
to compute and verify either CRC-16 or the CRC-
32 value within each inbound HDLC frame.
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