XRT72L53 Datasheet, PDF (63/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
áç
PRELIMINARY
A.0 Execute a Single Ordinary (Programmed I/
O) Read Cycle, as described in steps A.1
through A.8 below.
A.1 Assert the ALE_AS (AS*) input pin by toggling
it "Low". This step enables the Address Bus
input drivers (within the XRT72L53 DS3/E3
Framer) within the Framer Microprocessor
Interface Block.
A.2 Place the address of the initial target register or
buffer location (within the Framer), on the
Address Bus input pins, A[10:0].
A.3 At the same time, the Address-Decoding cir-
cuitry (within the user's system) should assert
the CS (Chip Select) input pins of the Framer
by toggling it "Low". This action enables further
communication between the µC/µP and the
Framer Microprocessor Interface block.
A.4 After allowing the data on the Address Bus pins
to settle (by waiting the appropriate Address
Setup time), the µC/µP should toggle the
ALE_AS input pin "High". This step causes the
Framer to latch the contents of the Address Bus
into its internal circuitry. At this point, the initial
address of the burst access has now been
selected.
A.5 Further, the µC/µP should indicate that this
cycle is a Read cycle by setting the WR_R/W
(R/W*) input pin "High".
A.6 Next the µC/µP should initiate the current bus
cycle by toggling the RD_DS (Data Strobe)
input pin "Low". This step will enable the bi-
directional data bus output drivers, within the
XRT72L53 DS3/E3 Framer. At this point, the bi-
directional data bus output drivers will proceed
to driver the contents of the Address register
onto the bi-directional data bus.
A.7 After some settling time, the data on the bi-
directional data bus will stabilize and can be
read by the µC/µP. The XRT72L53 DS3/E3
Framer will indicate that this data can be read
by asserting the RDY_DTCK (DTACK) signal.
A.8 After the µC/µP detects the RDY_DTCK signal
(from the XRT72L53 DS3/E3 Framer) it will ter-
minate the Read Cycle by toggling the RD_DS
(Data Strobe) input pin "High".
Figure 33 presents an illustration of the behavior of
the Microprocessor Interface Signals during the initial
Read Operation, within a Burst I/O Cycle, for a Motor-
ola-type µC/µP.
FIGURE 33. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE INITIAL READ OPERATION OF A
BURST CYCLE (MOTOROLA TYPE PROCESSOR)
ALE_AS
A(10:0)
CS
D(7:0)
RD_DS
WR_R/W
RDY_DTCK
Address of "Initial" Target Register (Offset = 0x00)
Not Valid
Valid Data at
Offset = 0x00
At the completion of this initial read cycle, the µC/µP
has read in the contents of the first register or buffer
location (within the XRT72L53 DS3/E3 Framer) for
this particular burst access operation. In order to illus-
trate how this burst I/O cycle works, the byte (or word)
of data, that is being read in Figure 33 has been la-
beled Valid Data at Offset = “0x00”. This indicates
that the µC/µP is reading the very first register (or
buffer location) in this burst access.
2.3.2.2.2.1.2 The Subsequent Read Operations
63