XRT72L53 Datasheet, PDF (15/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
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PRELIMINARY
PIN DESCRIPTION CONNECTED PINS
PIN #
D9
PIN NAME
ExtLOS[0]
D10 RxOHEnable[1]/
RxHDLCDat5[1]
D11
VDD
D12
RxOHClk[0]/
TYPE
I
O
****
O
DESCRIPTION
Receive LOS (Loss of Signal) Indicator Input - Channel 0 (from the
DS3/E3 LIU IC):
This input pin is intended to be connected to the RLOS (Receive Loss
of Signal) output pin of the DS3/E3 Line Interface Unit IC. The user can
monitor the state of this pin by reading the state of Bit 0 (RLOS0) within
the Line Interface Scan Register (Address = 0x81).
If this input pin is "Low", then it means that the LIU device is currently
NOT declaring an LOS (Loss of Signal) condition. However, if this input
pin is "High", then it means that the LIU device is currently declaring an
LOS (Loss of Signal) condition.
Asserting the RLOS input pin will cause the Receive Section of Channel
0 to declare an LOS (Loss of Signal) condition. Therefore, this input pin
should not be used as a general purpose input.
Receive Overhead Enable Indicator/Receive HDLC Controller Data
Output - Bit 5; Channel 1:
See Description for Pin B13
Power Supply +3.3v ± 5%
Receive Overhead Output Clock Signal/Receive HDLC Controller
Output Clock - Channel 0:
The exact function of this output pin depends upon whether Channel 0,
within the XRT72L53 device has been configured to operate in the
“High Speed HDLC Controller” Mode, or not.
RxHDLCClk[0]
D13
GND
D14
TxNib0[1]/
TxHDLCDat0[1]
D15
VDD
D16
TxNIBClk[1]/
SndFCS[1]
D17
GND
Non-High Speed HDLC Controller Mode - Receive Overhead Out-
put Clock Signal - Channel 0:
Channel 0, within the XRT72L53 device will output the Overhead bits
(within the incoming DS3 or E3 frames), via the RxOH[0] output pin,
upon the falling edge of this clock signal.
As a consequence, the user's data link equipment should use the rising
edge of this clock signal to sample the data on both the RxOH[0] and
RxOHFrame[0] output pins.
NOTE: This clock signal is always active.
High Speed HDLC Controller Mode - Receive HDLC Output Clock -
Channel 0:
When the HDLC controller is on, RxHDLCDat is updated by the 72L53
on this clock signal.
****
Ground
I
Transmit Nibble-Parallel Payload Data Input - Bit 0/Transmit HDLC
Data Input - Bit 0; Channel 1:
See Description for Pin D18
****
Power Supply +3.3v ± 5%
O
Transmit Nibble Clock output signal/Transmit HDLC - SEND Frame
I
Check Sequence - Channel 1:
See Description for Pin F18
****
Ground
15