XRT72L53 Datasheet, PDF (135/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RxDS3/E3
Interrupt
Status
Not Used
RO
RO
RO
RO
RO
0
0
0
0
0
BIT 2
RO
0
BIT 1
TxDS3/E3
Interrupt
Status
RO
0
BIT 0
One-Second
Interrupt
Status
RO
0
The Block Interrupt Status Register presents the in-
terrupt request status of each functional block, within
the chip. The purpose of the Block Interrupt Status
Register is to help the local µP/µC identify which func-
tional block(s) has requested the interrupt. Whichever
bit(s) are asserted in this register, identifies which
block(s) have experienced an interrupt-generating
condition as presented in Table 6. Once the local µP/
µC has read this register, it can determine which
branch within the interrupt service routine that it must
follow, in order to properly service this interrupt.
The Framer further supports the Functional Block hi-
erarchy by providing the Block Interrupt Enable Reg-
ister (Address = 0x04). The bit format of this register
is identical to that for the Block Interrupt Status regis-
ter, and is presented below for the sake of complete-
ness.
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxDS3/E3
Interrupt
Status
Not Used
TxDS3/E3
Interrupt
Status
One-Second
Interrupt
Status
R/W
RO
RO
RO
RO
RO
R/W
R/W
0
0
0
0
0
0
0
0
The Block Interrupt Enable register allows the user to
individually enable or disable the interrupt requesting
capability of the functional blocks, within the Framer
IC. If a particular bit-field, within this register contains
the value "0", then the corresponding functional block
has been disabled from generating any interrupt re-
quests. Conversely, if that bit-field contains the value
"1", then the corresponding functional block has been
enabled for interrupt generation (e.g., those potential
interrupts, within the enabled functional block that are
enabled at the source level, are now enabled). The
user should be aware of the fact that each functional
block, within the Framer IC contains anywhere from 1
to 12 potential interrupt sources. Each of these lower
level interrupt sources contain their own set of inter-
rupt enable bits and interrupt status bits, existing in
various on-chip registers.
Interrupt Service Routing Branching: after read-
ing the Block Interrupt Status Register.
The contents of the Block Interrupt Status Register
identify which of 3 functional blocks (within the Fram-
er IC) has requested interrupt service. The local µP
should use this information in order to determine
where, within the Interrupt Service Routing, program
control should branch to. Table 10 can be viewed as
an interrupt service routine guide. It lists each of the
Functional Blocks, that contain a bit-field in the Block
Interrupt Status Register. Additionally, this table also
presents a list and addresses of corresponding on-
chip Registers that the Interrupt Service Routine
should branch to and read, based upon the Interrupt-
ing Functional Block.
Table 10, Table 11, and Table 12 presents the Inter-
rupt Service Routine guide for DS3, E3/ITU-T G.832
and E3/ITU-T G.751 applications, respectively.
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