XRT72L53 Datasheet, PDF (14/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
PIN DESCRIPTION CONNECTED PINS
PIN #
C20
PIN NAME
TxNib2[0]/
TYPE
I
DESCRIPTION
Transmit Nibble-Parallel Payload Data Input - Bit 2/Transmit HDLC
Data Input - Bit 2; Channel 0:
The exact function of this input pin depends upon whether Channel 0
has been configured to operate in the “High-Speed HDLC Controller”
Mode, or not.
TxHDLCDat2[0]
D1
TxNEG[0]
D2
TRST
D3
TMS
D4
GND
D5
RxOOF[1]
D6
VDD
D7
TAOS[1]
D8
GND
Non-High Speed HDLC Controller Mode - Transmit Nibble-Parallel
Payload Data Input -Bit 2; Channel 0:
The Terminal Equipment is expected to input data, that is intended to be
transmitted to the remote terminal, over an E3 or DS3 transport
medium. The Framer IC will take data, applied to this pin, and insert it
into an outbound E3 or DS3 frame. The XRT72L53 will sample the data
that is at these input pins, upon the rising edge of the TxNibClk signal.
NOTE: This input pin is active only if the Nibble-Parallel Mode has been
selected.
High Speed HDLC Controller Mode - Transmit HDLC Data Input -
Bit 2:
This pin functions as bit 2, within the byte-wide Transmit HDLC Control-
ler input interface (TxHDLCDat[7:0]), whenever Channel 0 has been
configured to operate in the “High-Speed HDLC Controller” Mode.
O
Transmit Negative Polarity Pulse output - Channel 0:
The exact role of this output pin depends upon whether Channel 0 is
operating in the Single-Rail or Dual-Rail Mode.
Single-Rail Mode:
This output signal pulses "High" for one bit period, at the end of each
outbound DS3 or E3 frame. This output signal is kept at a logic "Low" for
all of the remaining bit-periods of the outbound DS3 or E3 frames
Dual-Rail Mode:
This output pin functions as one of the two dual-rail output signals that
commands the sequence of pulses to be driven on the line. TxPOS[0] is
the other output pin. This input is typically connected to the TNDATA
input of the external DS3/E3 Line Interface Unit IC. When this output is
asserted, it will command the LIU to generate a negative polarity pulse
on the line.
I
JTAG Reset Pin:
Resets Boundary Scan Logic.
NOTE: For normal operation this input pin should be tied “low”.
I
Test Mode Select: Boundary Scan Mode Select input.
NOTE: For normal operation, this input pin should be tied “low”
****
Ground
O
Receive Out of Frame Indicator - Channel 1:
See Description for Pin A3
****
Power Supply +3.3v ± 5%
O
Transmit All Ones Signal (TAOS) Command Input - Channel 1 (fto
be connected to the “TAOS” input of the DS3/E3 LIU IC):
See Description for Pin C6
****
Ground
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