XRT72L53 Datasheet, PDF (132/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L53
REV. P1.1.7
Setting this bit-field to “0” configures the Transmit
HDLC Controller block to compute and append the
CRC-16 value to the end of the outbound HDLC
frame. Further, this setting also configures the Re-
ceive HDLC Controller block compute and verify the
CRC-32 value, which has been appended to the end
of the inbound HDLC frame.
Setting this bit-field to “1” configures the Transmit
HDLC Controller block to compute and append the
CRC-32 value to the end of the outbound HDLC
frame. Further, this same setting also configures the
Receive HDLC Controller block to compute and verify
the CRC-32 value, which has been appended to the
end of the inbound HDLC frame.
NOTE: This bit-field is only active if the channel has been
configured to operate in the High-Speed HDLC Controller
Mode.
Bit 3 - HDLC Loop-Back
2.5 THE LOSS OF CLOCK ENABLE FEATURE
The timing for the Microprocessor Interface section,
originates from a line rate (e.g., either a 34.368MHz
or 44.736 MHz) signal that is provided by either the
TxInClk[n] or the RxLineClk[n] signals. However, if the
Framer experiences a Loss of Clock signal event
such that neither the TxInClk[n] nor the RxLineClk[n]
signal are present, then the Framer Microprocessor
Interface section cease to function.
The Framer offers a Loss of Clock (LOC) protection
feature that allows the Microprocessor Interface sec-
tion to at least complete or terminate an in-process
Read or Write cycle (with the local µP) should this
Loss of Clock event occur. The LOC circuitry consists
of a ring oscillator that continuously checks for signal
transitions at the TxInClk[n] and RxLineClk[n] input
pins. If a Loss of Clock Signal event occur such that
no transitions are occurring on these pins, then the
LOC circuitry will automatically assert the
RDY_DTCK signal in order to complete (or terminate)
the current Read or Write cycle with the Framer Mi-
croprocessor Interface section.
This LOC Protection may be enabled or disabled fea-
ture by writing to Bit 7 (LOC Enable) within the Fram-
er I/O Register, as depicted below.
ADDRESS = 0X01, FRAMER I/O CONTROL REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOC Enable Test PMON
Interrupt
Enable
Reset
AMI/B3ZS*
Unipolar/
Bipolar*
TxLine
Clk Inv
RxLine
Clk Inv
Reframe
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
0
0
Writing a "1" to this bit-field enables this LOC Protec-
tion feature. Writing a "0" to this bit-field disables this
feature.
NOTE: The Ring Oscillator can be a source of noise, within
the Framer chip. Hence, there may be situations where the
user will wish to disable the LOC Protection feature.
2.6 USING THE PMON HOLDING REGISTER
The Microprocessor Interface section consists of an
8-bit bi-directional data bus. As a consequence, the
local µP will be able to read from and write to the
Framer on-chip registers, 8 bit per (read or write) cy-
cle. Since most of the Framer on-chip registers con-
tain 8-bits, communicating with the local µP, over an
8-bit data bus, is not much of an inconvenience. How-
ever, all of the PMON registers, within the Framer IC,
contain 16 bits. Consequently, any reads of the
PMON registers, will require two read cycles. To
make matters potentially more complicated, these
PMON registers are Reset-upon-Read registers.
Therefore, the contents of both the MSB and LSB
registers (of the READ PMON register) are reset to
zero upon the first of these two read cycles.
Fortunately, the XRT72L53 Framer IC includes a fea-
ture that will make reading a PMON register a slightly
less complicated task. The Framer chip address
space contains a read-only register known as the
PMON Holding register, which is located at 0x6C.
Whenever the local µP reads in an 8-bit value of a
given PMON registers (e.g., either the upper-byte or
the lower byte value of the PMON register), the other
8-bit value of that PMON register will automatically be
loaded into the PMON Holding register. As a conse-
quence, the other 8-bit value of the PMON register is
accessible by reading the PMON Holding register.
Hence, anytime the local µP is trying to read in the
contents of a PMON register, the first read access
must be made directly to one of the 8-bit values of the
PMON registers (e.g., for example: the PMON LCV
Event Count Register - MSB, Address = 0x50). How-
ever, the second read must always be made to a con-
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