XRT72L53 Datasheet, PDF (79/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
ister was read. This bit-field will be asserted under ei-
ther of the following conditions:
For DS3 Applications
1. When the Receive DS3/E3 Framer block detects
the occurrence of an LOS Condition (e.g., the
occurrence of 180 consecutive spaces in the
incoming DS3 data stream), and
2. When the Receive DS3/E3 Framer block detects
the end of an LOS Condition (e.g., when the
Receive DS3 Framer detects 60 mark pulses in
the last 180 bit periods).
For E3 Applications
3. When the Receive DS3/E3 Framer block detects
the occurrence of an LOS Condition (e.g., the
occurrence of 32 consecutive spaces in the
incoming E3 data stream).
4. When the Receive DS3/E3 Framer block detects
the end of an LOS Condition (e.g., the occur-
rence of 32 consecutive bits that does not contain
a string of 4 consecutive “0s”.
The local µP can determine the current state of the
LOS condition by reading bit 6 of the Rx DS3 Config-
uration and Status Register (Address = 0x10).
NOTE: For more information in the LOS of Signal (LOS)
Alarm, please see Section 3.3.2.5.1.
Bit 5 - AIS Interrupt Status
This Reset Upon Read bit field will be set to "1", if the
Receive DS3/E3 Framer block has detected a
Change in the AIS condition, since the last time this
register was read. This bit-field will be asserted under
either of the following two conditions:
1. When the Receive DS3/E3 Framer block first
detects an AIS Condition in the incoming DS3
data stream, and
2. When the Receive DS3/E3 Framer block has
detected the end of an AIS Condition.
The local µP can determine the current state of the
AIS condition by reading bit 7 of the Rx DS3 Configu-
ration and Status Register (Address = 0x10).
NOTE: For more information on the AIS Condition please
see Sections 3.3.2.5.2.
Bit 4 - Idle Interrupt Status
This Reset Upon Read bit-field is set to "1" when the
Receive DS3/E3 Framer block detects a Change in
the Idle Condition in the incoming DS3 data stream.
Specifically, the Receive DS3/E3 Framer block will as-
sert this bit-field under either of the following two con-
ditions:
1. When the Receive DS3/E3 Framer block detects
the onset of the Idle Condition and
2. When the Receive DS3/E3 Framer block detects
the end of the Idle Condition.
The local µP can determine the current state of the
Idle condition by reading bit 5 of the Rx DS3 Configu-
ration and Status Register (Address = 0x10).
NOTE: For more information into the Idle Condition, please
see Section 3.3.2.5.3.
Bit 3 - FERF Interrupt Status
This Reset Upon Read bit will be set to '1' if the Re-
ceive DS3/E3 Framer block has detected a Change in
the Rx FERF Condition, since the last time this regis-
ter was read.
This bit-field will be asserted under either of the fol-
lowing two conditions.
1. When the Receive DS3/E3 Framer block first
detects the occurrence of an Rx FERF Condition
(all X-bits are set to '0').
2. When the Receive DS3/E3 Framer block detects
the end of the Rx FERF Condition (all X-bits are
set to '0').
The local microprocessor can determine the current
state of the FERF Condition by reading bit 4, within
the Rx DS3 Status Register (Address = 0x11).
NOTE: For more information on the Rx FERF (Yellow
Alarm) condition, please see Section 3.3.2.5.4.
Bit 2 - (Change in) AIC Interrupt Status
This Reset Upon Read bit-field is set to "1" if the AIC
bit-field, within the incoming DS3 frames, has
changed state since the last read of this register.
NOTE: For more information on this interrupt condition,
please see Section 3.3.2.5.6.
Bit 1 - OOF Interrupt Status
This Reset Upon Read bit-field is set to "1" if the Re-
ceive DS3/E3 Framer block has detected a Change in
the Out-of-Frame (OOF) Condition, since the last time
this register was read. Therefore, this bit-field will be
asserted under either of the following two conditions:
1. When the Receive DS3/E3 Framer block has
detected the appropriate conditions to declare an
OOF Condition.
2. When the Receive DS3/E3 Framer block transi-
tions from the OOF Condition (Frame Acquisition
Mode) into the In-Frame Condition (Frame Main-
tenance mode).
NOTE: For more information of the OOF Condition, please
see Section 3.3.2.2.
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