XRT72L53 Datasheet, PDF (78/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L53
REV. P1.1.7
This Read/Write bit-field is used to enable or disable
the Detection of CP-Bit Error Interrupt. Setting this
bit-field to “1’ enables this interrupt. Setting this bit-
field to “0” disables this interrupt.
NOTES:
1. For more information on the CP-Bit Error Checking/
Detection, please see Section 3.3.2.6.2.
2. This bit-field is only valid if the Channel has been
configured to operate in the DS3, C-Bit Parity
Framing format.
Bit 6 - LOS Interrupt Enable
This Read/Write bit-field is used to enable or disable
the Change in LOS condition interrupt. Setting this
bit-field to "1" enables this interrupt. Setting this bit-
field to "0" disables this interrupt.
NOTE: For more information on the LOS Condition, please
see Sections 3.3.2.5.1.
Bit 5 - AIS Interrupt Enable
This Read/Write bit-field is used to enable or disable
the Change in AIS condition interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field
to "0" disables this interrupt.
NOTE: For more information on the AIS Condition, please
see Sections 3.3.2.5.2.
Bit 4 - Idle Interrupt Enable
This Read/Write bit-field is used to enable or disable
the Change in Idle condition interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field
to "0" disables this interrupt.
NOTE: For more information on the Idle Condition, please
see Section 3.3.2.5.3.
Bit 3 - FERF Interrupt Enable
This Read/Write bit-field is used to enable or disable
the Change in FERF (Far End Receive Failure) Status
interrupt. Setting this bit-field to "1" enables this inter-
rupt. Setting this bit-field to "0" disables this interrupt.
NOTE: For more information on Far-End Receive Failures
(or Yellow Alarms) please see Section 3.3.2.5.4.
Bit 2 - AIC Interrupt Enable
This Read/Write bit field allows the user to enable or
disable the Change in AIC value interrupt. Setting this
bit-field to "1" enables this interrupt. Setting this bit-
field to "0" disables this interrupt.
NOTE: For more information on this interrupt condition,
please see Section 3.3.2.5.6.
Bit 1 - OOF Interrupt Enable
This Read/Write bit field is used to enable or disable
the Change in Out-of-Frame (OOF) status interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
NOTE: For more information on the OOF' Condition, please
see Section 3.3.2.2.
Bit 0 - P-Bit Error Interrupt Enable
This Read/Write bit-field is used to enable or disable
the Detection of P-Bit Error interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field
to "0" disables this interrupt.
NOTE: For more information on the P-Bit Error Checking/
Detection, please see Section 3.3.2.6.1.
2.4.2.11 Receive DS3 Interrupt Status Register
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC
Interrupt
Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Bit 7 - CP Bit Error Interrupt Status
This Reset-upon-Read bit-field indicates whether or
not the Detection of CP Bit Error Interrupt has oc-
curred since the last read of this register. This bit-field
will be “0” if the Detection of CP-Bit Error Interrupt
has not occurred since the last read of this register.
Conversely, this bit-field will be set to “1” if this inter-
rupt has occurred since the last read of this register.
The Detection of CP Bit Error Interrupt will occur if the
Receive DS3/E3 Framer block detects a CP bit-error
in the incoming DS3 frame.
NOTE: This bit-field is only valid if the channel has been
configured to operate in the DS3, C-bit Parity Framing for-
mat.
Bit 6 - LOS Interrupt Status
This Reset Upon Read bit will be set to "1", if the Re-
ceive DS3/E3 Framer block has detected a Change in
the LOS Status condition, since the last time this reg-
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