XRT72L53 Datasheet, PDF (139/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
8051 Microcontroller IC and cannot be changed.
Table 14 presents the location (in code memory)
where the program control will branch to, if either of
these inputs are asserted.
TABLE 14: INTERRUPT SERVICE ROUTINE LOCATION (IN CODE MEMORY) FOR THE INT0* AND INT1* INTERRUPT
INPUT PINS
INTERRUPT PIN
BRANCH TO LOCATION (IN SYSTEM MEMORY)
INT0*
0x0003
INT1*
0x0013
Therefore, if either one of these inputs are used as an
interrupt request input, then the appropriate interrupt
service routine or unconditional branch instruction (to
the interrupt service routine) must be located at one
of these address locations.
If the 8051 Microcontroller IC is required to interface
to external components in the data memory space of
sizes greater than 256 bytes, then both Ports 0 and 2
must be used as the address and data lines. Port 0
will function as a multiplexed address/data bus. Dur-
ing the first half of a memory cycle, Port 0 will operate
as the lower address byte. During the second half of
the memory cycle, Port 0 will operate as the bi-direc-
tional data bus. Port 2 will be used as the upper ad-
dress byte. ALE and the use of a 74HC373 transpar-
ent latch can be used to de-multiplex the Address and
Data bus signals.
Figure 37 presents a schematic illustrating how the
XRT72L53 DS3/E3 Framer can be interfaced to the
8051 Microcontroller IC.
FIGURE 37. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT72L53 DS3/E3 FRAMER IC TO THE 8051 MICRO-
CONTROLLER
U4
WR
RD
16
17
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
39
38
37
36
35
34
33
32
HW_RESET*
U1
T19
P17
V20
RESET
WRB_RW
RDB_DS
L18
L20
K20
K19
K18
K17
J20
J19
D0
D1
D2
D3
D4
D5
D6
D7
INT0
INT1
12
13
ALE ³⁰
A8
A9
A10
A11
A12
A13
A14
A15
21
22
23
24
25
26
27
28
XRT72L53_INT*
5.0V
5.0V
A8
A9
ALE
A10
U3
3
4
7
8
13
14
17
18
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2
5
6
9
12
15
16
19
11
1
LE
OE
20 _VCC
74HC373
ALE
A8
A9
A10
XRT72L53_INT*
From Address Decoder
R19 _{ALE_AS}
R20
P18
P19
P20
N18
N19
N20
M17
M18
M19
M20
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
J17 _{Rdy_Dtck}
H20 _INT
R18 _CS
To Address Decoder
8051
T20
MOTO/INTEL
XRT72L53
The circuitry in Figure 37 will function as follows, dur-
ing a Framer-request interrupt. The Framer would re-
quest an interrupt from the CPU by asserting its ac-
tive low INT output pin. This will cause the INT0* input
pin of the CPU to go "Low”. When this happens the
8051 CPU will finish executing its current instruction,
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