XRT72L53 Datasheet, PDF (74/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L53
REV. P1.1.7
this bit-field to "0" does disable all Receive Section related
Interrupts.
Bit 1 - TxDS3/E3 Interrupt Enable
This Read/Write bit-field is used to enable or disable
all Transmit Section related interrupts (within the
XRT72L53), at the Block Level.
Setting this bit-field to "0" disables all Transmit Sec-
tion related Interrupts within the XRT72L53.
Setting this bit-field to "1" enables the Transmit Sec-
tion related Interrupts (within the XRT72L53) at the
block level.
NOTE: Setting this bit-field to "1" does not enable all Trans-
mit Section related Interrupts. Each of these interrupts can
still be disabled at the Source Level. However, setting this
bit-field to "0" does disable all Transmit Section related
Interrupts.
Bit 0 - One-Second Interrupt Enable
This Read/Write bit-field is used to enable or disable
the One-Second Interrupt, within the XRT72L53. If
this interrupt is enabled, then the XRT72L53 will gen-
erate interrupts to the µC/µP at one-second intervals.
Setting this bit-field to "0" disables the One-Second
Interrupt. Conversely, setting this bit-field to "1" en-
ables the One-Second Interrupt.
2.4.2.6 Block Interrupt Status Register
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxDS3/E3
Interrupt
Status
Not Used
TxDS3/E3
Interrupt
Status
One-Second
Interrupt
Status
RO
RO
RO
RO
RO
RO
RO
RUR
0
0
0
0
0
0
0
0
Bit 7 - RxDS3/E3 Interrupt Status Indicator
This Read-Only bit-field indicates whether or not a
Receive-Section related interrupt has been requested
and is awaiting service.
If this bit-field is set to "0", then there are no Receive-
Section related interrupts awaiting service. Converse-
ly, if this bit-field is set to "1", then there is at least one
Receive Section related interrupt, awaiting service.
NOTE: If this bit-field is set to "1", then the µC/µP must
read the Source-Level Interrupt Status register, in order to
clear this bit-field.
Bit 1 - TxDS3/E3 Interrupt Status Indicator
This Read-Only bit-field indicates whether or not a
Transmit-Section related interrupt has been request-
ed and is awaiting service.
If this bit-field is set to "0", then there are no Transmit-
Section related interrupts awaiting service. Converse-
ly, if this bit-field is set to "1", then there is at least one
Transmit Section related interrupt, awaiting service.
NOTE: If this bit-field is set to "1", then the µC/µP must
read the Source-Level Interrupt Status register, in order to
clear this bit-field.
Bit 0 - One-Second Interrupt Status
This Reset-upon-Read bit field indicates whether or
not a One-Second interrupt has been requested and
is awaiting service.
If this bit-field is set to "0", then the One-Second inter-
rupt is not awaiting service. Conversely, if this bit-field
is set to "1", then the One-Second interrupt is await-
ing service.
NOTE: This bit-field will be cleared immediately after the
µC/µP has read this register.
2.4.2.7 Test Register
TEST REGISTER (ADDRESS = 0X0C)
BIT 7
TxOH
Source
Select
BIT 6
Rx
Payload
Clock
Enable
BIT 5
Tx
Payload
Clock
Enable
BIT 4
Rx
PRBS
Lock
BIT 3
Rx
PRBS
Enable
BIT 2
Tx
PRBS
Enable
BIT 1
BIT 0
Reserved
R/W
R/W
R/W
RO
R/W
R/W
RO
RUR
0
0
0
0
0
0
0
0
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