XRT72L53 Datasheet, PDF (298/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.8
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
Disable TxLOC
BIT 6
LOC
R/W
RO
1
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup*
R/W
0
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
0
0
BIT 0
Reframe
R/W
0
Table 58 relates the content of this bit-field to the Bi-
polar Line Code that E3 Data will be transmitted and
received at.
TABLE 58: THE RELATIONSHIP BETWEEN BIT 4 (AMI/
HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE
BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT
E3 LIU INTERFACE BLOCK
BIT 4
0
1
BIPOLAR LINE CODE
HDB3
AMI
NOTES:
1. This bit is ignored if the Unipolar mode is selected.
2. This selection also effects the operation of the
Receive E3 LIU Interface block
5.2.5.2 TxLineClk Clock Edge Selection
The Framer also allows the user to specify whether
the E3 output data (via TxPOS and/or TxNEG output
pins) is to be updated on the rising or falling edges of
the TxLineClk signal. This selection is made by writ-
ing to bit 2 of the I/O Control Register, as depicted be-
low.
II/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
Disable TxLOC
BIT 6
LOC
R/W
RO
1
0
BIT 5
Disable
RxLOC
R/W
1
BIT 4
AMI/ZeroSup*
R/W
0
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
BIT 1
TxLine CLK RxLine CLK
Invert
Invert
R/W
R/W
0
0
BIT 0
Reframe
R/W
0
Table 59 relates the contents of this bit field to the
clock edge of TxClk that E3 Data is output on the Tx-
POS and/or TxNEG output pins.
TABLE 59: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 2
0
1
RESULT
Rising Edge:
Outputs on TxPOS and/or TxNEG are updated on the rising edge of TxLineClk.
See Figure 125 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.
Falling Edge:
Outputs on TxPOS and/or TxNEG are updated on the falling edge of TxLineClk.
See Figure 126 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.
NOTE: The user will typically make the selection based
upon the set-up and hold time requirements of the Transmit
LIU IC.
298