XRT72L53 Datasheet, PDF (462/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.1.8
TABLE 94: DESCRIPTION OF EACH OF THE TRANSMIT HDLC CONTROLLER PINS
PIN NAME
Snd_Msg_n
Snd_FCS_n
TxHDLCClk_n
TxHDLCDat_n[7:0]
TYPE
I
I
O
I
DESCRIPTION
Send Message Command:
This input pin permits the user to command the Transmit HDLC Controller block to
begin sampling and latching the data, which is being applied to the TxHDLCDat_n[7:0]
input pins.
If the user pulls this input pin "High", then the Transmit HDLC Controller block will
begin to sample and latch the data (which is applied to the TxHDLCDat_n[7:0] input
pins), upon the rising edge of TxHDLCClk_n. Each byte of this sampled data will ulti-
mately be encapsulated into an outbound HDLC Frame.
If the user pulls this input pin "Low", then the Transmit HDLC Controller block will NOT
sample and latch data (which is residing on the TxHDLCDat_n[7:0] input pins. As a
consequence, no outbound HDLC Frames will be generated, and the Transmit HDLC
Controller block will simply generate a constant stream of Flag Sequence octets
(0x7E).
Send Frame Check Sequence Command:
The user’s terminal equipment is expected to control both this input pin, along with the
Snd_Msg_n input pin, during the construction and transmission of each outbound
HDLC frame.
This input pin permits the user to command the Transmit HDLC Controller block to
compute and insert the compute FCS (Frame-Check Sequence) value into the back-
end of the outbound HDLC frame, as a trailer.
If the user has configured the Transmit HDLC Controller to compute and insert a CRC-
16 value into the outbound HDLC frame, then the terminal equipment is expected to
pull this input pin "High" for two periods of TxHDLCClk_n.
Conversely, if the user has configured the Transmit HDLC Controller to compute and
insert a CRC-32 value into the outbound HDLC frame, then the terminal equipment is
expected to pull this input pin "High" for four periods of TxHDLCClk_n.
Transmit HDLC Controller Clock Output signal:
This output signal functions as the demand clock for the Transmit HDLC Controller.
When the user pulls the Snd_Msg_n input pin "High", then the Transmit HDLC Con-
troller block will begin to sample and latch the contents of the TxHDLCDat_n[7:0] upon
the rising edge of this clock signal. As a consequence, the user is advised to design/
configure their terminal equipment circuitry to output data (onto the
TxHDLCDat_n[7:0] bus), upon the falling edge of this clock signal.
Since the Transmit HDLC Controller block is sampling and latching 8-bits of data at a
given time, it may be presumed that the frequency of the TxHDLCClk_n output signal
is either 34.368MHz/8 or 44.736MHz/8. In general, this presumption is true. However,
because the Transmit HDLC Controller is also performing “0” stuffing of the user data
that it receives from the Terminal Equipment, the frequency of this signal may be
slower.
Transmit HDLC Controller - Input Data Bus:
These eight input pins function as the byte-wide input interface to the Transmit HDLC
Controller. If the user pulls the Snd_Msg_n input pin "High", then the Transmit HDLC
Controller block will begin to sample and latch the contents of this data bus, into the
Transmit HDLC Controller circuitry (upon the rising edge of TxHDLCClk_n). All data
that is sampled, via this byte-wide interface will ultimately be encapsulated into an out-
bound HDLC Controller.
If the user pulls the Snd_Msg_n input pin "Low", then the Transmit HDLC Controller
block will ignore the data that is being applied to this data bus.
Whenever the user wishes to transmit data via the
Transmit HDLC Controller block, then he/she should
pull the Snd_Msg_n input pin "High". Once the
Snd_Msg_n pin is pulled high, then the Transmit
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