XRT72L53 Datasheet, PDF (362/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.8
The XRT72L53 will receive the E3 payload data, in a
serial manner, via the TxSer input pin. The Transmit
Payload Data Input Interface (within the XRT72L53)
will latch this data into its circuitry, on the rising edge
of the TxInClk input clock signal.
C. Delineation of Outbound DS3 frames (Frame
Master Mode)
The Transmit Section of the XRT72L53 will use the
TxInClk signal as its timing reference, and will initiate
E3 frame generation, asynchronously with respect to
any externally applied signal. The XRT72L53 will
pulse its TxFrame output pin "High" whenever its it
processing the very last bit-field within a given E3
frame.
D. Sampling of payload data, from the Terminal
Equipment
In Mode 3, the XRT72L53 will sample the data, at the
TxSer input pin, on the rising edge of TxInClk.
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT72L53 to the Terminal Equip-
ment for Mode 3 Operation
Figure 161 presents an illustration of the Transmit
Payload Data Input Interface block (within the
XRT72L53) being interfaced to the Terminal Equip-
ment, for Mode 3 operation.
FIGURE 161. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT72L53 FOR MODE 3 (SERIAL/LOCAL-TIMED/FRAME-MASTER) OPERATION
34.368 MHz
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Clock Source
E3_Clock_In
E3_Clock_In
E3_Data_Out
E3_Data_Out
TxStart_of_Frame
TxStart_of_Frame
E3_Overhead_Ind
E3_Overhead_Ind
TxInClk
TxInClk
TxSer
TxSer
TxFrameRef
TxFrameRef
TxOH_Ind
TxOH_Ind
NibInt
NibInt
Terminal Equipment
XRT72L5X E3 Framer
Mode 3 Operation of the Terminal Equipment
In Figure 161, both the Terminal Equipment and the
XRT72L53 are driven by an external 34.368 MHz
clock signal. This clock signal is connected to the
E3_Clock_In input of the Terminal Equipment and the
TxInClk input pin of the XRT72L53.
The Terminal Equipment will serially output the pay-
load data on its E3_Data_Out output pin, upon the
rising edge of the signal at the E3_Clock_In input pin.
Similarly, the XRT72L53 will latch the data, residing
on the TxSer input pin, on the rising edge of TxInClk.
The XRT72L53 will pulse the TxFrame output pin
"High" for one bit-period, coincident while it is pro-
cessing the last bit-field within a given Outbound E3
frame. The Terminal Equipment is expected to moni-
tor the TxFrame signal (from the XRT72L53) and to
place the first bit, within the very next Outbound E3
frame on the TxSer input pin.
NOTE: In this case, the XRT72L53 dictates exactly when
the very next E3 frame will be generated. The Terminal
Equipment is expected to respond appropriately by provid-
ing the XRT72L53 with the first bit of the new E3 frame,
upon demand. Hence, in this mode, the XRT72L53 is
referred to as the Frame Master and the Terminal Equip-
ment is referred to as the Frame Slave.
Finally, the XRT72L53 will pulse its TxOH_Ind output
pin, one bit-period prior to it processing a given over-
head bit, within the Outbound E3 frame. Since the
TxOH_Ind output pin of the XRT72L53 is electrically
connected to the E3_Overhead_Ind whenever the
XRT72L53 pulses the TxOH_Ind output pin "High", it
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