XRT72L53 Datasheet, PDF (133/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
stant location in system memory, the PMON Holding
Register.
2.7 THE INTERRUPT STRUCTURE WITHIN THE FRAMER
MICROPROCESSOR INTERFACE SECTION
The XRT72L53 Framer is equipped with a sophisti-
cated Interrupt Servicing Structure. This Interrupt
Structure includes an Interrupt Request output, INT,
numerous Interrupt Enable Registers and numerous
Interrupt Status Registers. The Interrupt Servicing
Structure, within each of the three channels contains
two levels of hierarchy. The top level is at the function-
al block level (e.g., the Receive Section, the Transmit
Section, etc.). The lower hierarchical level is at the in-
dividual interrupt or source level. Each hierarchical
level consists of a complete set of Interrupt Status
Registers/bits and Interrupt Enable Registers/bits, as
will be discussed below.
Both of the functional sections, within each channel,
are capable of generating Interrupt Requests to the
local µP/µC. The Framer Interrupt Structure has been
carefully designed to allow the user to quickly deter-
mine the exact source of the interrupt (with minimal
latency) which will aid the local µP/µC in determining
which interrupt service routine to call up in order to
respond to or eliminate the condition(s) causing the
interrupt.
Table 6 lists all of the possible conditions that can
generate interrupts, with each functional section of a
given channel.
TABLE 6: LIST OF ALL OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS WITHIN EACH CHANNEL OF
THE XRT72L53 FRAMER
FUNCTION SECTION
INTERRUPTING CONDITION
Transmit Section
FEAC Message Transfer Complete (DS3, C-Bit Parity Only)
LAPD Message frame Transfer Complete (DS3, C-Bit Parity, All E3)
Receive Section
Change of Status on Receive LOS, OOF, AIS Idle Detection
Validation and removal of received FEAC Code (DS3, C-Bit Parity Only)
New PMDL Message in Receive LAPD Message Buffer.
Detection of Parity Errors (e.g., P-Bit, CP-Bit, BIP-4 and BIP-8 Errors)
Detection of Framing Bit/Byte Errors.
Framer Chip Level One-Second Interrupt
Each of the three channels, within the XRT72L53
Framer contains an Interrupt Block that comes
equipped with the following registers to support the
servicing of these potential interrupt request sources.
Table 7, 8 , and 9 lists these registers, and their ad-
dresses, within the Framer IC for DS3, E3 (ITU-T
G.832) and E3 (ITU-T G.751) framing formats.
TABLE 7: A LISTING OF THE XRT72L53 FRAMER INTERRUPT BLOCK REGISTERS (FOR DS3 APPLICATIONS)
ADDRESS LOCATION
REGISTER NAME
0 x 04
Block Interrupt Enable Register
0 x 05
Block Interrupt Status Register
0 x 12
RxDS3 Interrupt Enable Register
0 x 13
RxDS3 Interrupt Status Register
0 x 17
RxDS3 FEAC Interrupt Enable/Status Register
0 x 18
RxDS3 LAPD Control Register
0 x 31
TxDS3 FEAC Configuration and Status Register
0 x 34
TxDS3 LAPD Status/Interrupt Register
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