XRT72L53 Datasheet, PDF (265/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.8
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PRELIMINARY
XRT72L53 will indicate that it is processing the last
nibble, within a given E3 frame, by pulsing its TxNib-
Frame output pin "High" for one TxNibClk clock peri-
od. When the Terminal Equipment detects a pulse at
its Tx_Start_of_Frame input pin, it is expected to
transmit the first nibble, of the very next outbound E3
frame to the XRT72L53 via the E3_Data_Out[3:0] (or
TxNib[3:0] pins).
Finally, for the Nibble-Parallel Mode operation, the
XRT72L53 will pulse the TxOHInd output pin "High”
for 3 nibble-periods (e.g., the 3 nibbles consisting of
the 10 bit FAS pattern, the “A” and the “N” bits). The
TxOHInd output pin will remain "Low” for the remain-
der of the frame period. The TxOHInd output pin will
toggle "High” one-nibble period before the Transmit
Section (of the Framer IC) processes the first four bits
of the FAS pattern.
The behavior of the signals between the XRT72L53
and the Terminal Equipment for E3 Mode 4 Operation
is illustrated in Figure 107.
FIGURE 107. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT72L53 AND THE TERMINAL
EQUIPMENT (MODE 4 OPERATION)
Terminal Equipment Signals
RxOutClk
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
Payload Nibble [380]
Overhead Nibble [0]
XRT72L5x Transmit Payload Data I/F Signals
RxOutClk
TxNibClk
TxNib[3:0]
TxNibFrame
Nibble [380]
Overhead Nibble [0]
TxOH_Ind
Note: TxNibFrame pulses high to denote
E3 Frame Boundary.
E3 Frame Number N
E3 Frame Number N + 1
TxOH_Ind pulses high for 3 Nibble periods
How to configure the XRT72L53 into Mode 4
1. Set the NibIntf input pin "High".
2. Set the TimRefSel[1:0] bit-fields (within the
Framer Operating Mode Register) to "00" as illus-
trated below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
Local
Loopback
R/W
0
BIT 6
DS3/E3*
R/W
0
BIT 5
Internal
LOS
Enable
R/W
1
BIT 4
RESET
R/W
0
BIT 3
Interrupt
Enable
Reset
R/W
1
BIT2
Frame
Format
R/W
0
BIT 1
BIT 0
TimRefSel[1:0]
R/W
R/W
0
0
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