XRT72L53 Datasheet, PDF (368/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.8
3. Interface the XRT72L53, to the Terminal Equip-
ment, as illustrated in Figure 165.
6.2.1.6 Mode 6 - The Nibble-Parallel/Local-
Timed/Frame-Master Interface Mode Behavior of
the XRT72L53
If the XRT72L53 has been configured to operate in
this mode, then the XRT72L53 will function as fol-
lows:
A. Local Timing - Uses the TxInClk signal as the
Timing Reference
In this mode, the Transmit Section of the XRT72L53
will use the TxInClk signal at its timing reference. Fur-
ther, the chip will internally divide the TxInClk clock
signal by a factor of 4 and will output this divided
clock signal via the TxNibClk output pin. The Transmit
Terminal Equipment Input Interface block (within the
XRT72L53) will use the rising edge of the TxNibClk
signal, to latch the data, residing on the TxNib[3:0] in-
to its circuitry.
B. Nibble-Parallel Mode
The XRT72L53 will accept the E3 payload data, from
the Terminal Equipment, in a parallel manner, via the
TxNib[3:0] input pins. The Transmit Terminal Equip-
ment Input Interface will latch this data into its circuit-
ry, on the rising edge of the TxNibClk output signal.
C. Delineation of Outbound E3 Frames
The Transmit Section will use the TxInClk input signal
as its timing reference and will initiate the generation
of E3 frames, asynchronous with respect to any ex-
ternal signal. The XRT72L53 will pulse the TxFrame
output pin "High" whenever it is processing the last
bit, within a given Outbound E3 frame.
D. Sampling of payload data, from the Terminal
Equipment
In Mode 6, the XRT72L53 will sample the data, at the
TxNib[3:0] input pins, on the third rising edge of the
TxInClk clock signal, following a pulse in the TxNibClk
signal (see Figure 168).
NOTE: The TxNibClk signal, from the XRT72L53 operates
nominally at 8.592 MHz (e.g., 34.368 MHz divided by 4).
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT72L53 to the Terminal Equip-
ment for Mode 6 Operation
Figure 167 presents an illustration of the Transmit
Payload Data Input Interface block (within the
XRT72L53) being interfaced to the Terminal Equip-
ment, for Mode 6 Operation.
FIGURE 167. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT72L53 FOR MODE 6 OPERATION
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
34.368MHz Clock Source
8.592MHz
4
TxInClk
TxNibClk
TxNib[3:0]
TxNibFrame
TxOH_Ind
NibInt
VCC
Terminal Equipment
XRT72L5x E3 Framer
Mode 6 Operation of the Terminal Equipment
In Figure 167 both the Terminal Equipment and the
XRT72L53 will be driven by an external 8.592MHz
clock signal. The Terminal Equipment will receive the
8.592MHz clock signal via the E3_Nib_Clock_In input
pin. The XRT72L53 will output the 8.592MHz clock
signal via the TxNibClk output pin.
The Terminal Equipment will serially output the data
on the E3_Data_Out[3:0] pins upon the rising edge of
the signal at the E3_Clock_In input pin. The
XRT72L53 will latch the data, residing on the Tx-
Nib[3:0] input pins, on the rising edge of the TxNibClk
signal.
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