XRT72L53 Datasheet, PDF (122/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L53
REV. P1.1.7
FAS of each outbound E3 frame. The user may wish
to do this for equipment testing purposes. Prior to
transmission, the Transmit E3 Framer block reads in
the upper five (5) bits of the FAS value, and performs
an XOR operation with it and the contents of this reg-
ister. The results of this operation are written back in-
to the upper five (5) bits of the FAS value, in each out-
bound E3 frame. Consequently, to insure errors are
not injected into the FAS of the outbound E3 frames,
the contents of this register must be set to all "0’s"
(the default value).
2.4.7.6 Transmit E3 FAS Error Mask Register -
1 (ITU-T G.751)
TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
TxFAS_Error_Mask_Lower[4:0]
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 4 - 0, TxFAS_Error_Mask_Lower[4:0]
This Read/Write bit-field is used to insert errors into
the lower five bits of the Framing Alignment Signal,
FAS of each outbound E3 frame. The user may wish
to do this for equipment testing purposes. Prior to
transmission, the Transmit E3 Framer block reads in
the lower five (5) bits of the FAS value, and performs
an XOR operation with it and the contents of this reg-
ister. The results of this operation are written back in-
to the lower five (5) bits of the FAS value, in each out-
bound E3 frame. Consequently, to insure errors are
not injected into the FAS of the outbound E3 frames,
the contents of this register must be set to all "0’s"
(the default value).
2.4.7.7 Transmit E3 BIP-4 Error Mask Register
(ITU-T G.751)
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
TxBIP-4 Mask[3:0]
R/W
R/W
0
0
BIT 0
R/W
0
Bits 3 - 0: TxBIP-4 Mask[3:0]
This Read/Write bit-field is used to insert errors into
the BIP-4 value within each outbound E3 frame. The
user may wish to do this for equipment testing pur-
poses. Prior to transmission, the Transmit DS3/E3
Framer block reads in the BIP-4 value, and performs
an XOR operation with it and the contents of this reg-
ister. The results of this operation are written back in-
to the BIP-4 nibble position, in each outbound E3
frame. Consequently, to insure errors are not injected
into the BIP-4 value of the outbound E3 frames, the
contents of this register must be set to all "0’s" (the
default value).
NOTE: This register is ignored if Bit 7 (Tx BIP-4 Enable)
within the TxE3 Configuration register (Address = 0x30) is
set to “0”.
2.4.8 Performance Monitor Registers
2.4.8.1 PMON Line Code Violation Count Reg-
ister - MSB
PMON LCV EVENT COUNT REGISTER - MSB (ADDRESS = 0X50)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LCV Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
122