XRT72L53 Datasheet, PDF (64/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L53
REV. P1.1.7
The procedure that the µC/µP must use to perform
the remaining read cycles, within this Burst Access
operation, is presented below.
B.0 Execute each subsequent Read Cycle, as
described in steps B.1 through B.3, below.
B.1 Without toggling the ALE_AS input pin (e.g.,
keeping it "High"), toggle the RD_DS (Data
Strobe) input pin "Low". This step accom-
plishes the following.
a. The Framer internally increments the latched
address value (within the Microprocessor Inter-
face circuitry).
b. The output drivers of the bi-directional data bus
(D[7:0]) are enabled. At some time later, the reg-
ister or buffer location corresponding to the incre-
mented latched address value will be driven onto
the bi-directional data bus.
NOTE: In order to insure that the XRT72L53 DS3/E3
Framer will interpret this signal as being a Read signal, the
µC/µP should keep the WR_R/W input pin "High".
B.2 After some settling time, the data on the bi-
directional data bus will stabilize and can be
read by the µC/µP. The XRT72L53 DS3/E3
Framer will indicate that this data is ready to be
read by asserting the RDY_DTCK (DTACK*)
signal.
B.3 After the µC/µP detects the RDY_DTCK signal
(from the XRT72L53 DS3/E3 Framer), it termi-
nates the Read cycle by toggling the RD_DS
(Data Strobe) input pin "High".
For subsequent read operations, within this burst cy-
cle, the µC/µP simply repeats steps B.1 through B.3,
as illustrated in Figure 34.
FIGURE 34. BEHAVIOR THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT READ OPERATIONS
WITHIN THE BURST I/O CYCLE (MOTOROLA-TYPE µC/µP)
ALE_AS
A(10:0)
Address of "Initial" Target Register (Offset = 0x00)
CS
D(7:0)
RD_DS
Not Valid
Valid Data at
Offset = 0x01
Not Valid
Valid Data at
Offset = 0x02
WR_R/W
RDY_DTCK
2.3.2.2.2.1.3 Terminating the Burst Access
Operation
The Burst I/O Access will be terminated upon the fall-
ing edge of the ALE_AS input signal. At this point the
Framer will cease to internally increment the latched
address value. Further, the µC/µP is now free to exe-
cute either a Programmed I/O access or to start an-
other Burst Access Operation with the XRT72L53
DS3/E3 Framer.
2.3.2.2.2.2 The Motorola-Mode Write Burst
Access
Whenever a Motorola-type µC/µP wishes to write the
contents of numerous registers or buffer locations
over a contiguous range of addresses, then it should
do the following.
a. Perform the initial write operation of the burst
access.
b. Perform the remaining write operations, of the
burst access.
c. Terminate the burst access operation.
Each of these operations within the burst access are
described below.
2.3.2.2.2.2.1 The Initial Write Operation
The initial write operation of a Motorola-type Write
Burst Access is accomplished by executing a Pro-
grammed I/O Write Cycle as summarized below.
64