XRT72L53 Datasheet, PDF (269/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.8
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PRELIMINARY
FIGURE 110. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK OF THE XRT72L53 FOR MODE 6 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-MASTER)
OPERATION
E3_Nib_Clock_In
E3_Data_Out[3:0]
Tx_Start_of_Frame
E3_Overhead_Ind
34.368MHz Clock Source
8.592MHz
4
TxInClk
TxNibClk
TxNib[3:0]
TxNibFrame
TxOH_Ind
NibInt
VCC
Terminal Equipment
XRT72L5x E3 Framer
Mode 6 Operation of the Terminal Equipment
In Figure 110 both the Terminal Equipment and the
XRT72L53 will be driven by an external 8.592MHz
clock signal. The Terminal Equipment will receive the
8.592MHz clock signal via the E3_Nib_Clock_In input
pin. The XRT72L53 will output the 8.592MHz clock
signal via the TxNibClk output pin.
The Terminal Equipment will serially output the data
on the E3_Data_Out[3:0] pins upon the rising edge of
the signal at the E3_Clock_In input pin. The
XRT72L53 will latch the data, residing on the Tx-
Nib[3:0] input pins, on the rising edge of the TxNibClk
signal.
In this case the XRT72L53 has the responsibility of
providing the framing reference signal by pulsing the
TxFrame output pin (and in turn the
Tx_Start_of_Frame input pin of the Terminal Equip-
ment) "High" for one bit-period, coincident with the
last bit within a given E3 frame.
Finally, the XRT72L53 will always internally generate
the Overhead bits, when it is operating in both the E3
and Nibble-parallel modes. The XRT72L53 will pull
the TxOHInd input pin "Low".
The behavior of the signals between the XRT72L53
and the Terminal Equipment for E3 Mode 6 Operation
is illustrated in Figure 111.
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