XRT72L53 Datasheet, PDF (128/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L53
REV. P1.1.7
This Read-Only register, along with the Frame CP-Bit
Error - One-Second Accumulator Register - LSB (Ad-
dress = 0x73) contains a 16-bit representation of the
number of CP Bit Errors that have been detected by
the Receive DS3/E3 Framer block, within the last
one-second sampling period. This register contains
the MSB (or Upper Byte) value of this 16-bit expres-
sion.
NOTE: This register is only active if the Channel has been
configured to operate in the DS3, C-bit Parity framing for-
mat.
2.4.8.18 One-Second Frame CP-Bit Error Accu-
mulator Register - LSB
FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X73)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error Count - Low Byte
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
This Read-Only register, along with the Frame CP-Bit
Error - One-Second Accumulator Register - MSB (Ad-
dress = 0x72) contains a 16-bit representation of the
number of CP Bit Errors that have been detected by
the Receive DS3/E3 Framer block, within the last
one-second sampling period. This register contains
the LSB (or Lower Byte) value of this 16-bit expres-
sion.
NOTE: This register is only active if the Channel has been
configured to operate in the DS3, C-bit Parity framing for-
mat.
2.4.8.19 Line Interface Drive Register
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REQ
TAOS
ENCODIS
TxLEV
RLOOP
LLOOP
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
0
0
0
Bit 5 - REQ - (Receive Equalization Bypass Con-
trol)
This Read/Write bit-field is used to control the state of
the REQ output pin of the Framer. This output pin is
intended to be connected to either the REQ or the
REQEN input pin of the DS3/E3 LIU IC.
If the user connects the REQ output pin of the Framer
to either the REQDIS or the REQEN input pin of the
DS3/E3 LIU IC, then the user will have Microproces-
sor Control over the state of the Receive Equalizer
within the DS3/E3 LIU IC.
Writing a "1" to this bit-field causes the Channel to
toggle the REQ output pin "High". Writing a "0" to this
bit-field causes the Channel to toggle the REQ output
pin "Low".
NOTE: If the customer is not using an Exar XRT73L0X
DS3/E3/STS-1 LIU IC, then this bit-field and the REQ out-
put pin can be used for other purposes.
Bit 4 - TAOS - (Transmit All Ones Signal)
This Read/Write bit-field is used to control the state of
the TAOS output pin of the Framer. This output pin is
intended to be connected to the TAOS input pin of the
DS3/E3 LIU IC. If the user forces this signal to toggle
"High", then the LIU will transmit an "All Ones" pattern
onto the line. Conversely, if the user commands this
output signal to toggle "Low" then the LIU IC will pro-
ceed to transmit data based upon the pattern that it
receives via the TxPOS[n] and TxNEG[n] output pins
(of the Framer IC).
Writing a "1" to this bit-field will cause the TAOS[n]
output pin to toggle "High". Writing a "0" to this bit-
field will cause this output pin to toggle "Low".
NOTE: If the customer is not using an Exar XRT73L0X
DS3/E3/STS-1 LIU IC, then this bit-field, and the TAOS out-
put pin can be used for other purposes.
Bit 3 - Encodis - (B3ZS Encoder Disable)
This Read/Write bit-field allows the user to control the
state of the Encodis output pin of the Framer. This
output pin is intended to be connected to either the
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