XRT72L53 Datasheet, PDF (65/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
A.0 Execute a Single Ordinary (Programmed I/
O) Write cycle, as described in Steps A.1
through A.7 below.
A.1 Assert the ALE_AS (Address Strobe) input pin
by toggling it "Low". This step enables the
Address Bus input drivers (within the
XRT72L53 DS3/E3 Framer).
A.2 Place the address of the initial target register or
buffer location (within the Framer), on the
Address Bus input pins, A[10:0].
A.3 At the same time, the Address-Decoding cir-
cuitry (within the user's system) should assert
the CS input pin of the Framer by toggling it
"Low". This step enables further communica-
tion between the µC/µP and the Framer Micro-
processor Interface block.
A.4 After allowing the data on the Address Bus pins
to settle (by waiting the appropriate Address
Setup time), the µC/µP should toggle the
ALE_AS input pin "High". This step causes the
Framer to latch the contents of the Address Bus
into its own circuitry. At this point, the initial
address of the burst access has now been
selected.
A.5 Further, the µC/µP should indicate that this cur-
rent bus cycle is a Write operation by toggling
the WR_R/W (R/W*) input pin "Low".
A.6 The µC/µP should then place the byte or word
that it intends to write into the target register, on
the bi-directional data bus, D[7:0].
A.7 Next, the µC/µP should initiate the bus cycle by
toggling the RD_DS (Data Strobe) input pin
"Low". When the XRT72L53 DS3/E3 Framer
senses that the WR_R/W input pin is "Low", and
that the RD_DS input pin has toggled "Low" it
will enable the input drivers of the bi-directional
data bus, D[7:0].
A.8 After waiting the appropriate amount of time, for
this newly placed data to settle on the bi-direc-
tional data bus (e.g., the Data Setup time) the
Framer will assert the RDY_DTCK (DTACK)
output signal.
A.9 After the µP/µC detects the RDY_DTCK signal
(from the Framer) it should toggle the RD_DS
input pin "High". This action accomplishes two
things:
a. It latches the contents of the bi-directional data
bus into the XRT72L53 DS3/E3 Framer Micropro-
cessor Interface block.
b. It terminates the Write cycle.
Figure 35 presents a timing diagram which illustrates
the behavior of the Microprocessor Interface signals,
during the Initial write operation within a Burst Ac-
cess, for a Motorola-type µC/µP.
FIGURE 35. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE INITIAL WRITE OPERATION OF
A BURST CYCLE (MOTOROLA-TYPE PROCESSOR)
ALE_AS
A(10:0)
CS
D(7:0)
RD_DS
WR_R/W
RDY_DTCK
Address of "Initial" Target Register (Offset = 0x00)
Data to be Written
(Offset = 0x00)
At the completion of this initial write cycle, the µC/µP
has written a byte or word into the first register or
buffer location (within the XRT72L53 DS3/E3 Framer)
for this particular burst I/O access. In order to illus-
trate how this burst I/O cycle works, the byte (or word)
of data, that is being written in Figure 35 has been la-
beled Data to be Written (Offset = 0x00).
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