XRT72L53 Datasheet, PDF (142/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L53
REV. P1.1.7
control over many aspects of the XRT7300 DS3/E3/
STS-1 LIU IC without having to develop the neces-
sary off-chip glue-logic.
Figure 39 presents a simple circuit schematic that de-
picts how the XRT72L53 DS3/E3 Framer IC could be
interfaced to the XRT7300 DS3/E3/STS-1 LIU IC.
FIGURE 39. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT72L53 DS3/E3 FRAMER IC TO THE XRT73L03
DS3/E3/STS-1 LIU IC (ONE CHANNEL SHOWN)
RxAVDD_0
DVDD_0
Rx_AIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
Rx_LOS_Ch_0
RxFRAME_0
RxFRAME_CLK_0
RxDATA_IN_0
D[7:0]
A[10:0]
READY_OUT*
ALE
RD*
WR*
XRT72L53_CS*
XRT72L53_INT*
HW_RESET*
R9
100
TxFRAME_0
44.736MHz
TxDATA_OUT_0
U19
C5
B5
A3
C4
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
F20
D20
F19
T20
RxFrame_0
RxClk_0
RxSer_0
MOTO
RxPOS_0 ^F2
RxNEG_0 ^F3
J19
J20
K17
K18
K19
K20
L20
L18
D7
D6
D5
D4
D3
D2
D1
D0
M20
M19
M18
M17
N20
N19
A10
A9
A8
A7
A6
N18
P20
P19
A5
A4
A3
P18
R20
A2
A1
A0
J17
R19
V20
Rdy_Dtck
ALE_AS
P17
R18
H20
RDB_DS
WRB_RW
CSB
INT
T19 _RESETB
F1
RxLineClk_0
RLOL_0
ExtLOS_0
B8
D9
LLOOP_0
REQB_0
TAOS_0
DMO_0
C7
A5
C6
C9
C3
TxLEV_0
RLOOP_0 ^B7
ENCODIS_0 (TxOFF_0) ^B2
TxPOS_0 ^C1
TxNEG_0 ^D1
TxLineClk_0 ^E2
T18 _NIBBLEINTF
E20
G4
E18
TxFrame_0
TxInClk_0
TxSER_0
XRT72L53_Ch_0
C2
0.01uF
C3
0.01uF
R8 4.7K
R7 100
70
RxAVDD0
48 _RxDVDD0
67
42
LOSTHR_0
HOST/HW
51 _RPOS0
50 _RNEG0
49
RCLK0
U21
28
TxAVDD0
TxAVDD0 ³⁷
RTIP0 ⁷²
71
RRING0
XRT71D03_CS* (Optional)
57
55
RLOL_0
RLOS_0
61
62
63
64
96
CS
SCLK
SDI
SDO
REG_RESET*
117 _{TxOFF_0}
33 _{TPDATA_0}
32 _{TNDATA_0}
34
47
TCLK_0
EXCLK_0
TTIP0 ²⁹
TRING0 ²⁷
30
MTIP0
54 _RxDGND0
73 _RxAGND0
MRING0 ³¹
TxAGND0 ³⁹
TxAGND0 ²⁶
XRT73L03IV_Ch_0
C4
0.01uF
TxAVDD_0
C5
0.01uF
R2
R1
37.4
37.4
C1
0.01uF
6 _T2 1
43
T3001
R3
1 _T1 6
36
R4
34
T3001
R5
36
270
R6
270
J1
BNC
1
J2
BNC
1
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE
REGISTER
As mentioned above, the Line Interface Drive and
Scan section consists of five output pins and three in-
put pins. The logic state of the output pins are con-
trolled by the contents within the Line Interface Drive
register, as depicted below.
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ILOOP
REQ
TAOS
ENCODIS
TXLEV
RLOOP
LLOOP
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
0
0
0
The role of each of these bit-fields are their corre-
sponding output pins are depicted below.
Bit 7 - ILOOP (Internal Remote Loop-back)
This Read/Write bit-field allows configuring the corre-
sponding channel (within the XRT72L53) to operate
in the Internal Remote Loop-back Mode. Once the
channel is configured to operate in this remote loop-
back mode, then the RxPOS[n], RxNEG[n] and RxLi-
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