XRT72L53 Datasheet, PDF (47/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.8
áç
PRELIMINARY
FIGURE 19. MICROPROCESSOR INTERFACE TIMING - INTEL TYPE READ BURST ACCESS OPERATION
ALE_AS
A[10:0]
CS
D[7:0]
RD_DS
WR_R/W
RDY_DTCK
t₇₆
Address of “Initial” Target Register (Offset = 0x00)
t₆₈
Not Valid Valid Data at Offset =0x01
Not Valid Valid Data at Offset =0x02
t₇₀
FIGURE 20. MICROPROCESSOR INTERFACE TIMING - INTEL TYPE WRITE BURST ACCESS OPERATION
ALE_AS
A(10:0)
Address of Initial Target Register (offset = 0x00)
CS
D(7:0)
RD_DS
WR_R/W
Not Valid
Valid Data at
Offset = 0x01
t₆₈
t₇₆
Not Valid
Valid Data at
Offset = 0x02
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