XRT72L53 Datasheet, PDF (5/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
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PRELIMINARY
PIN DESCRIPTION CONNECTED PINS
PIN #
A13
PIN NAME
RxOHFrame[0]/
RxHDLCDat4[0]
A14
TxOHClk[0]
A15
TxOH[0]/
TYPE
O
O
I
DESCRIPTION
Receive Overhead Frame Boundary Indicator/Receive HDLC Con-
troller Data Output - Bit 4
The exact functionality of this output pin depends upon whether Chan-
nel 0 has been configured to operate in the “High Speed HDLC Control-
ler” Mode, or not.
Non-High Speed HDLC Controller Mode - Receive Overhead Frame
Boundary Indicator:
This output pin pulses "High" whenever the Receive Overhead Data
Output Interface” block outputs the first overhead bit (or nibble) of a new
DS3 or E3 frame.
High Speed HDLC Controller Mode - Receive HDLC Data Output -
Bit 4:
This pin functions as bit 4, within the byte-wide Receive HDLC Control-
ler output interface (RxHDLCDat[7:0]), whenever Channel 0 has been
configured to operate in the “High Speed HDLC Controller” Mode.
Transmit Overhead Clock output - Channel 0:
This output signal serves two purposes:
1. The Transmit Overhead Data Input Interface block will provide a rising
clock edge on this signal, one bit-period prior to the start to the instant
that the “Transmit Overhead Data Input Interface” block (associated with
Channel 1) is processing an overhead bit.
2. The Transmit Overhead Data Input Interface will sample the data at
the “TxOH[0]” input pin, on the falling edge of this clock signal (provided
that the “TxOHIns[0]” input pin is “HIGH”).
NOTE: The Transmit Overhead Data Input Interface block will supply a
clock edge for all overhead bits within the DS3 or E3 frame (via the
“TxOHClk[0]” output signal). This includes those overhead bits that the
“Transmit Overhead Data Input Interface” will not accept from the Termi-
nal Equipment.
Transmit Overhead Input Pin/Transmit HDLC Controller Data Input
- Bit 5 (Channel 0):
The exact functionality of this input pin depends upon whether Channel
0 has been configured to operate in the “High-Speed HDLC Controller”
Mode, or not.
TxHDLCDat5[0]
Non-High Speed HDLC Controller Mode - Transmit Overhead Input
pin - Channel 0:
The Transmit Overhead Data Input Interface accepts the overhead data
via this input pin, and inserts into the overhead bit position within the
very next outbound DS3 or E3 frame. If the TxOHIns pin is pulled
"High", then the Transmit Overhead Data Input Interface will sample the
data at this input pin (TxOH[0]), on the falling edge of the TxOHClk[0]
output pin. Conversely, if the TxOHIns[0] pin is pulled "Low", then the
Transmit Overhead Data Input Interface will NOT sample the data at this
input pin (TxOH[0]). Consequently, this data will be ignored.
High Speed HDLC Controller Mode - Transmit HDLC Data Input -
Bit 5:
This pin functions as bit 5, within the byte-wide Transmit HDLC Control-
ler input interface (TxHDLCDat[7:0]), whenever Channel 0 has been
configured to operate in the “High Speed HDLC Controller” Mode.
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