XRT72L53 Datasheet, PDF (125/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
This Reset-upon-Read register, along with the PMON
FEBE Event Count Register - MSB (Address = 0x56)
contains a 16-bit representation of the number of
FEBE Events that have been detected by the Receive
DS3/E3 Framer block, since the last read of these
registers. This register contains the LSB (or Lower-
Byte) value of this 16 bit expression.
2.4.8.9 PMON CP-Bit Error Event Count Regis-
ter - MSB
PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON
CP-Bit Error Count Register - LSB (Address = 0x59)
contains a 16-bit representation of the number of CP-
bit Errors that have been detected by the Receive
DS3/E3 Framer block (within the channel), since the
last read of these registers. This register contains the
MSB (or Upper-Byte) value of this 16 bit expression.
NOTE: This register is only active if the Channel has been
configured to operate in the DS3, C-bit Parity Framing for-
mat.
2.4.8.10 PMON CP-Bit Error Event Count Regis-
ter - LSB
PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This Reset-upon-Read register, along with the PMON
CP-Bit Error Count Register - MSB (Address = 0x58)
contains a 16-bit representation of the number of CP-
bit Errors that have been detected by the Receive
DS3/E3 Framer block (within the channel), since the
last read of these registers. This register contains the
LSB (or Lower-Byte) value of this 16 bit expression.
NOTE: This register is only active if the Channel has been
configured to operate in the DS3, C-bit Parity Framing for-
mat.
2.4.8.11 PMON Holding Register
PMON HOLDING REGISTER (ADDRESS = 0X6C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PMON Holding Value
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
Each of the above-defined PMON registers are 16 bit
Reset-upon-Read registers. However, the bi-drection-
al data bus (of the Framer IC) is only 8-bits wide. As a
consequence, whenever the Microprocessor intends
to read a PMON register, there are two things to bear
in mind.
1. This Microprocessor is going to require two read
accesses in order read out the full 16-bit expres-
sion of these PMON registers.
2. The entire 16-bit expression (of a given PMON
register) is going to be reset to 0x0000, immedi-
ately after the Microprocessor has completed its
first read access to the PMON register.
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