XRT72L53 Datasheet, PDF (75/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
Bit 7 - TxOH Source Select
This Read/Write bit-field is used to configure the
Transmit Section of the channel to accept overhead
bits/bytes via the TxSer[n] or TxNib[3:0][n] input pins.
Setting this bit-field to “1” configures the Transmit
Section of the channel to accept overhead bits/bytes
via either the TxSer[n] or TxNib[3:0][n]input pins.
Setting this bit-field to “0” configures the Transmit
Section of the channel to either internally generate or
accept the overhead bits/bytes via the TxOH[n] input
pin.
Bit 6 - Rx Payload Clock Enable
This Read/Write bit-field is used to configure the Re-
ceive Payload Data Output Interface block to output
the receive data in a gapped-clock manner. If the user
chooses this option, then the Receive Payload Data
Output Interface will only generate a clock edge (via
the RxClk[n] output pin) whenever a payload bit is be-
ing output via the RxSer[n] output pin. The Receive
Payload Data Output Interface will not generate a
clock edge (via the RxClk[n] output pin) whenever an
overhead bit is being output via the RxSer[n] output
pin.
If the user does not select this option then the Re-
ceive Payload Data Output Interface block will gener-
ate a clock edge for all bits (payload and overhead);
as they are output via the RxSer[n] output pin. How-
ever, the Receive Payload Data Output Interface will
also pulse the RxOHInd[n] output pin “High” each
time an overhead bit is being output via the RxSer[n]
output pin.
Setting this bit-field to “1” enables this feature. Setting
this bit-field to “0” disables this feature.
Bit 5 - Tx Payload Clock Enable
This Read/Write bit-field is used to configure the TxO-
HInd[n] output pin to function as either of the following
roles.
1. The Transmit Overhead Data Output Indicator
2. The Transmit Payload Data Clock Output signal.
If the TxOHInd[n] output pin is configured to function
as the Transmit Overhead Data Output signal, then
this output pin will pulse “High” one bit-period prior to
the instant that the Transmit Section of the channel
(within the XRT72L53) is processing an overhead bit.
If the TxOHInd[n] output pin is configured to function
as the Transmit Payload Data Clock output signal,
then the Transmit Payload Data Output interface
block will generate a clock edge via the TxOHInd[n]
output pin. The Local Terminal equipment is expected
to output outbound payload data to the Transmit Pay-
load Data Input Interface block (via the TxSer[n] input
pin) upon the falling edge of this clock signal.
NOTE: In this mode, the TxOHInd[n] output pin will not gen-
erate a clock edge, whenever the Transmit Section of the
XRT72L53 is about to process an overhead bit.
Setting this bit-field to “0” configures the TxOHInd[n]
output pin to function as the Transmit Overhead Data
Output signal. Setting this bit-field to “1” configures
the TxOHInd[n] output pin to function as the Transmit
Payload Data Clock output signal.
Bit 4 - Rx PRBS Lock
This Read-Only bit-field indicates whether or not the
PRBS Receiver has acquired PRBS Lock (or Pattern
Sync) with the data generated by the PRBS Genera-
tor.
If this bit-field is set to “1”, then the PRBS Receiver
has acquired PRBS lock with the data generated by
the PRBS Generator. If this bit-field is set to “0”, then
the PRBS Receiver has NOT acquired PRBS Lock
with the data generated by the PRBS Generator.
NOTE: This bit-field is only valid if both the RxPRBS Enable
and Tx PRBS Enable bit-fields are both set to “1”.
Bit 3 - Rx PRBS Enable
This Read/Write bit-field is used to enable the PRBS
Receiver within the channel.
Setting this bit-field to “1” enables the PRBS Receiver
within the channel. Setting this bit-field to “0” disables
the PRBS Receiver.
Bit 2 - Tx PRBS Enable
This Read/Write bit-field is used to enable the PRBS
Generator within the channel.
Setting this bit-field to “1” enables the PRBS Genera-
tor within the channel. Setting this bit-field to “0” dis-
ables the PRBS Generator.
Receive DS3 Framer Configuration Registers
2.4.2.8 Receive DS3 Configuration & Status
Register
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