XRT72L53 Datasheet, PDF (24/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
PIN DESCRIPTION CONNECTED PINS
PIN #
G19
PIN NAME
RxNib0[0]/
TYPE
O
DESCRIPTION
Receive Nibble Output - Bit 0/Receive HDLC Data - Bit 0, Channel
0:
The exact function of this input pin depends upon whether Channel 0 is
operating in the “High-Speed HDLC Controller” Mode, or not.
RxHDLCDat0[0]
G20
RxNib1[0]/
RxHDLCDat1[0]
H1
TxLineClk[1]
H2
RxLineClk[1]
H3
RxPOS[1]
H4
GND
H17
GND
Non-High Speed HDLC Controller Mode - Receive Nibble Output -
Bit 0:
The Receive Section of Channel 0 will output Received data (from the
Remote Terminal) to the local Terminal Equipment via this pin along
with RxNib1[0], RxNib2[0] and RxNib3[0].
The data at this pin is updated on the rising edge of the RxClk[0] output
signal.
NOTE: This output pin is active only if the Nibble-Parallel Mode has
been selected.
Receive HDLC Data Output - Bit 0:
This output pin functions as Bit 0 (the LSB) within the byte-wide Receive
HDLC Controller output interface (RxHDLCDat[7:0]), whenever Channel
0 has been configured to operate in the “High-Speed HDLC Controller”
Mode.
O
Receive Nibble Output - Bit 1/Receive HDLC Data - Bit 1; Channel
0:
The exact function of this input pin depends upon whether Channel 0 is
operating in the “High-Speed HDLC Controller” Mode, or not.
Non-High-Speed HDLC Controller Mode - Receive Nibble Output -
Bit 1:
The Receive Section of Channel 0 will output Received data (from the
Remote Terminal) to the local Terminal Equipment via this pin along
with RxNib0[0], RxNib2[0] and RxNib3[0].
The data at this pin is updated on the rising edge of the RxClk[0] output
signal.
NOTE: This output pin is active only if the Nibble-Parallel Mode has
been selected.
Receive HDLC Data Output - Bit 1:
This output pin functions as Bit 1 within the byte-wide Receive HDLC
Controller output interface (RxHDLCDat[7:0]), whenever Channel 0 has
been configured to operate in the “High-Speed HDLC Controller” Mode.
O
Transmit Line Interface Clock output - Channel 1:
See Description for Pin E2
I
Receiver LIU (Recovered) Clock input - Channel 1:
See Description for Pin F1
I
Receive Positive Data Input - Channel 1:
See Description for Pin F2
****
Ground
****
Ground
24