XRT72L53 Datasheet, PDF (8/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
PIN DESCRIPTION CONNECTED PINS
PIN #
B13
PIN NAME
RxOHEnable[0]/
TYPE
O
DESCRIPTION
Receive Overhead Enable Indicator/Receive HDLC Controller Data
Output - Bit 5; Channel 0:
The exact functionality of this output pin depends upon whether Chan-
nel 0 has been configured to operate in the “High-Speed HDLC Control-
ler” Mode, or not.
RxHDLCDat5[0]
B14 TxOHEnable[0]/
Non-High Speed HDLC Controller Mode - Receive Overhead
Enable Indicator - Channel 0:
The XRT72L53 will assert this output signal for one “RxOutClk” period
when it is safe for the Terminal Equipment to sample the data on the
“RxOH” output pin.
High-Speed HDLC Controller Mode - Receive HDLC Controller Data
Ouptut - Bit 5, Channel 0:
This pin functions as bit 5, within the byte-wide Receive HDLC Control-
ler output interface (RxHDLCDat[7:0]), whenever Channel 0 has been
configured to operate in the “High-Speed HDLC Controller” Mode.
O
Transmit Overhead Input Enable/Transmit HDLC Controller Data
Output - Bit 7; Channel 0:
The exact functionality of this bit-field depends upon whether Channel 0
has been configured to operate in the “High-Speed HDLC Controller”
Mode, or not.
TxHDLCDat7[0]
B15
TxAISEn[0]
B16
TxNib3[1]/
TxHDLCDat3[1]
Non-High Speed HDLC Controller Mode - Transmit Overhead Input
Enable Output - Channel 0:
Channel 0, within the XRT72L53 device, will assert this signal, for one
“TxInClk[0]” period, just prior to the instant that the “Transmit Overhead
I
Data Input Interface” will be sampling and processing an overhead bit.
If the Terminal Equipment intends to insert its own value for an over-
head bit, into the outbound DS3 or E3 frame, it is expected to sample
the state of this signal, upon the falling edge of “TxInClk”. Upon sam-
pling the “TxOHEnable” high, the Terminal Equipment should (1) place
the desired value of the overhead bit, onto the “TxOH” input pin and (2)
assert the “TxOHIns” input pin. The Transmit Overhead Data Input Inter-
face” block will sample and latch the data on the “TxOH” signal, upon
the rising edge of the very next “TxInClk” input signal.
High-Speed HDLC Controller Mode - Transmit HDLC Data Input -
Bit 7; Channel 0:
This pin functions as bit 5, within the byte-wide Transmit HDLC Control-
ler input interface (TxHDLCDat[7:0]), whenever Channel 0 has been
configured to operate in the “High-Speed HDLC Controller” Mode.
I
Transmit AIS Command Input - Channel 0:
Setting this input pin "High" configures the Transmit Section of Channel
0 to generate and transmit an AIS Pattern.
Setting this input pin "Low" configures the Transmit Section to generate
E3 or DS3 traffic in a normal manner.
I
Transmit Nibble-Parallel Payload Data Input - Bit 3/Transmit HDLC
Data Input - Bit 3; Channel 1:
See Description for Pin D19
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